diff options
Diffstat (limited to 'src/backends/reference')
10 files changed, 137 insertions, 115 deletions
diff --git a/src/backends/reference/RefLayerSupport.cpp b/src/backends/reference/RefLayerSupport.cpp index cbc6723dbc..81e5c837a5 100644 --- a/src/backends/reference/RefLayerSupport.cpp +++ b/src/backends/reference/RefLayerSupport.cpp @@ -794,20 +794,6 @@ bool RefLayerSupport::IsBatchToSpaceNdSupported(const TensorInfo& input, supported &= CheckSupportRule(TypesAreEqual(input, output), reasonIfUnsupported, "Reference BatchToSpaceNd: input and output types mismatched."); - supported &= CheckSupportRule(TensorNumDimensionsAreCorrect(output, 4), - reasonIfUnsupported, - CreateIncorrectDimensionsErrorMsg(4, - output.GetNumDimensions(), - batchToSpaceNdLayerStr, - outputTensorStr).data()); - - supported &= CheckSupportRule(TensorNumDimensionsAreCorrect(input, 4), - reasonIfUnsupported, - CreateIncorrectDimensionsErrorMsg(4, - input.GetNumDimensions(), - batchToSpaceNdLayerStr, - inputTensorStr).data()); - return supported; } diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp index 8b89743870..6e697723e9 100644 --- a/src/backends/reference/test/RefLayerTests.cpp +++ b/src/backends/reference/test/RefLayerTests.cpp @@ -1938,16 +1938,19 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwcFloat32, SpaceToBatchNdSim ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiChannelsNhwcFloat32, SpaceToBatchNdMultiChannelsNhwcFloat32Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiBlockNhwcFloat32, SpaceToBatchNdMultiBlockNhwcFloat32Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdPaddingNhwcFloat32, SpaceToBatchNdPaddingNhwcFloat32Test) +ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwc3DFloat32, SpaceToBatchNdSimpleNhwc3DFloat32Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwcFloat16, SpaceToBatchNdSimpleNhwcFloat16Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiChannelsNhwcFloat16, SpaceToBatchNdMultiChannelsNhwcFloat16Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiBlockNhwcFloat16, SpaceToBatchNdMultiBlockNhwcFloat16Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdPaddingNhwcFloat16, SpaceToBatchNdPaddingNhwcFloat16Test) +ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwc3DFloat16, SpaceToBatchNdSimpleNhwc3DFloat16Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwcUint8, SpaceToBatchNdSimpleNhwcUint8Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiChannelsNhwcUint8, SpaceToBatchNdMultiChannelsNhwcUint8Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiBlockNhwcUint8, SpaceToBatchNdMultiBlockNhwcUint8Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdPaddingNhwcUint8, SpaceToBatchNdPaddingNhwcUint8Test) +ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleNhwc3DUint8, SpaceToBatchNdSimpleNhwc3DUint8Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdSimpleUint16, SpaceToBatchNdSimpleUint16Test) ARMNN_AUTO_TEST_CASE_WITH_THF(SpaceToBatchNdMultiChannelsUint16, SpaceToBatchNdMultiChannelsUint16Test) @@ -1967,6 +1970,7 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_4, BatchToSpaceNdNhwcTes ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_5, BatchToSpaceNdNhwcTest5<DataType::Float32>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_6, BatchToSpaceNdNhwcTest6<DataType::Float32>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_7, BatchToSpaceNdNhwcTest7<DataType::Float32>) +ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat32_3D, BatchToSpaceNdNhwcTest8<DataType::Float32>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_1, BatchToSpaceNdNhwcTest1<DataType::Float16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_2, BatchToSpaceNdNhwcTest2<DataType::Float16>) @@ -1975,6 +1979,7 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_4, BatchToSpaceNdNhwcTes ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_5, BatchToSpaceNdNhwcTest5<DataType::Float16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_6, BatchToSpaceNdNhwcTest6<DataType::Float16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_7, BatchToSpaceNdNhwcTest7<DataType::Float16>) +ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcFloat16_3D, BatchToSpaceNdNhwcTest8<DataType::Float16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt1, BatchToSpaceNdNhwcTest1<DataType::QAsymmS8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt2, BatchToSpaceNdNhwcTest2<DataType::QAsymmS8>) @@ -1983,6 +1988,7 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt4, BatchToSpaceNdNhwcTest4<D ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt5, BatchToSpaceNdNhwcTest5<DataType::QAsymmS8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt6, BatchToSpaceNdNhwcTest6<DataType::QAsymmS8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt7, BatchToSpaceNdNhwcTest7<DataType::QAsymmS8>) +ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcInt_3D, BatchToSpaceNdNhwcTest8<DataType::QAsymmS8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint1, BatchToSpaceNdNhwcTest1<DataType::QAsymmU8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint2, BatchToSpaceNdNhwcTest2<DataType::QAsymmU8>) @@ -1991,6 +1997,7 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint4, BatchToSpaceNdNhwcTest4< ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint5, BatchToSpaceNdNhwcTest5<DataType::QAsymmU8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint6, BatchToSpaceNdNhwcTest6<DataType::QAsymmU8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint7, BatchToSpaceNdNhwcTest7<DataType::QAsymmU8>) +ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcUint_3D, BatchToSpaceNdNhwcTest8<DataType::QAsymmU8>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_1, BatchToSpaceNdNhwcTest1<DataType::QSymmS16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_2, BatchToSpaceNdNhwcTest2<DataType::QSymmS16>) @@ -1999,6 +2006,7 @@ ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_4, BatchToSpaceNdNhwcTe ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_5, BatchToSpaceNdNhwcTest5<DataType::QSymmS16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_6, BatchToSpaceNdNhwcTest6<DataType::QSymmS16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_7, BatchToSpaceNdNhwcTest7<DataType::QSymmS16>) +ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNhwcQsymm16_3D, BatchToSpaceNdNhwcTest8<DataType::QSymmS16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwFloat16_1, BatchToSpaceNdNchwTest1<DataType::Float16>) ARMNN_AUTO_TEST_CASE_WITH_THF(BatchToSpaceNdNchwFloat16_2, BatchToSpaceNdNchwTest2<DataType::Float16>) diff --git a/src/backends/reference/workloads/BatchToSpaceNd.cpp b/src/backends/reference/workloads/BatchToSpaceNd.cpp index bf7de1b04c..ebe9d2cfd5 100644 --- a/src/backends/reference/workloads/BatchToSpaceNd.cpp +++ b/src/backends/reference/workloads/BatchToSpaceNd.cpp @@ -1,85 +1,105 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017-2020,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "BatchToSpaceNd.hpp" -#include "RefWorkloadUtils.hpp" - -#include <armnn/Types.hpp> - -#include <armnn/utility/Assert.hpp> +#include <armnnUtils/DataLayoutIndexed.hpp> using namespace armnnUtils; namespace armnn { -inline unsigned int Offset(const TensorShape& shape, unsigned int batch, unsigned int height, unsigned int width, - unsigned int channels, const DataLayoutIndexed& dataLayout) +unsigned int Offset(const TensorShape& shape, + unsigned int batch, + unsigned int height, + unsigned int width, + unsigned int channels, + const DataLayoutIndexed& dataLayout) { - if (dataLayout.GetDataLayout() == DataLayout::NHWC) + // 3D Tensors + unsigned int channelDimension3D = dataLayout.GetDataLayout() == DataLayout::NCHW ? 1 : 2; + if (shape.GetNumDimensions() == 3) { - return ((batch * shape[dataLayout.GetHeightIndex()] + height) * shape[dataLayout.GetWidthIndex()] + width) * - shape[dataLayout.GetChannelsIndex()] + channels; + return (batch * shape[dataLayout.GetHeightIndex()] + height) * shape[channelDimension3D] + channels; + } + // 4D Tensors + else if (shape.GetNumDimensions() == 4) + { + if (dataLayout.GetDataLayout() == DataLayout::NHWC) + { + return ((batch * shape[dataLayout.GetHeightIndex()] + height) * + shape[dataLayout.GetWidthIndex()] + width) * + shape[dataLayout.GetChannelsIndex()] + channels; + } + else + { + return ((batch * shape[dataLayout.GetChannelsIndex()] + channels) * + shape[dataLayout.GetHeightIndex()] + height) * + shape[dataLayout.GetWidthIndex()] + width; + } } else { - return ((batch * shape[dataLayout.GetChannelsIndex()] + channels) * - shape[dataLayout.GetHeightIndex()] + height) * - shape[dataLayout.GetWidthIndex()] + width; + throw InvalidArgumentException("Tensor rank must be either 3 or 4", CHECK_LOCATION()); } } -void BatchToSpaceNd(const DataLayoutIndexed& dataLayout, - const TensorInfo& inputTensorInfo, - const TensorInfo& outputTensorInfo, - const std::vector<unsigned int>& blockShape, - const std::vector<std::pair<unsigned int, unsigned int>>& cropsData, - Decoder<float>& inputDecoder, - Encoder<float>& outputEncoder) +void BatchToSpaceNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const BatchToSpaceNdDescriptor& params, + Decoder<float>& inputData, + Encoder<float>& outputData) { - TensorShape inputShape = inputTensorInfo.GetShape(); - - ARMNN_ASSERT_MSG(inputShape.GetNumDimensions() == 4, "Expected Input with 4 Dimensions"); - - TensorShape outputShape = outputTensorInfo.GetShape(); + unsigned int rank = inputInfo.GetNumDimensions(); + if (rank != 3 && rank != 4 ) + { + throw InvalidArgumentException("Tensor rank must be either 3 or 4, but it is " + std::to_string(rank), + CHECK_LOCATION()); + } - ARMNN_ASSERT_MSG(outputShape.GetNumDimensions() == 4, "Expected Output with 4 Dimensions"); + DataLayoutIndexed dataLayout = params.m_DataLayout; + unsigned int channelDimension3D = params.m_DataLayout == DataLayout::NCHW ? 1 : 2; - const unsigned int inputBatchSize = inputShape[0]; - const unsigned int channels = inputShape[dataLayout.GetChannelsIndex()]; + TensorShape inputShape = inputInfo.GetShape(); + TensorShape outputShape = outputInfo.GetShape(); + const unsigned int inputBatchSize = inputShape[0]; const unsigned int outputBatchSize = outputShape[0]; - const unsigned int outputHeight = outputShape[dataLayout.GetHeightIndex()]; - const unsigned int outputWidth = outputShape[dataLayout.GetWidthIndex()]; - ARMNN_ASSERT_MSG(blockShape.size() > 0, "BlockShape must contain 1 or more entries"); + const unsigned int channels = (rank == 3) ? inputShape[channelDimension3D] + : inputShape[dataLayout.GetChannelsIndex()]; - const unsigned int blockShapeHeight = blockShape[0]; - const unsigned int blockShapeWidth = blockShape[1]; + const unsigned int inputHeight = inputShape[dataLayout.GetHeightIndex()]; + const unsigned int inputWidth = (rank == 3) ? 1 : inputShape[dataLayout.GetWidthIndex()]; + const unsigned int outputHeight = outputShape[dataLayout.GetHeightIndex()]; + const unsigned int outputWidth = (rank == 3) ? 1 : outputShape[dataLayout.GetWidthIndex()]; - ARMNN_ASSERT_MSG(cropsData.size() > 0, "Crops must contain 1 or more entries"); + const unsigned int blockHeight = params.m_BlockShape[0]; + const unsigned int blockWidth = (rank == 3) ? 1 : params.m_BlockShape[1]; - const unsigned int cropsTop = cropsData[0].first; - const unsigned int cropsLeft = cropsData[1].first; + const unsigned int cropsTop = params.m_Crops[0].first; + const unsigned int cropsLeft = (rank == 3) ? 0 : params.m_Crops[1].first; for (unsigned int inBatch = 0; inBatch < inputBatchSize; ++inBatch) { const unsigned int outBatch = inBatch % outputBatchSize; const unsigned int spatialOffset = inBatch / outputBatchSize; - for (unsigned int inH = 0; inH < inputTensorInfo.GetShape()[dataLayout.GetHeightIndex()]; ++inH) { - const unsigned int outH = inH * blockShapeHeight + spatialOffset / blockShapeWidth - cropsTop; + for (unsigned int inH = 0; inH < inputHeight; ++inH) + { + const unsigned int outH = inH * blockHeight + spatialOffset / blockWidth - cropsTop; if (outH >= outputHeight) { continue; } - for (unsigned int inW = 0; inW < inputTensorInfo.GetShape()[dataLayout.GetWidthIndex()]; ++inW) { - const unsigned int outW = inW * blockShapeWidth + spatialOffset % blockShapeWidth - cropsLeft; + for (unsigned int inW = 0; inW < inputWidth; ++inW) + { + const unsigned int outW = inW * blockWidth + spatialOffset % blockWidth - cropsLeft; if (outW >= outputWidth) { @@ -91,9 +111,9 @@ void BatchToSpaceNd(const DataLayoutIndexed& dataLayout, unsigned int outOffset = Offset(outputShape, outBatch, outH, outW, c, dataLayout); unsigned int inOffset = Offset(inputShape, inBatch, inH, inW, c, dataLayout); - outputEncoder[outOffset]; - inputDecoder[inOffset]; - outputEncoder.Set(inputDecoder.Get()); + outputData[outOffset]; + inputData[inOffset]; + outputData.Set(inputData.Get()); } } } diff --git a/src/backends/reference/workloads/BatchToSpaceNd.hpp b/src/backends/reference/workloads/BatchToSpaceNd.hpp index 0fcef58554..acacda4e86 100644 --- a/src/backends/reference/workloads/BatchToSpaceNd.hpp +++ b/src/backends/reference/workloads/BatchToSpaceNd.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017-2019,2021,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -9,21 +9,15 @@ #include "Decoders.hpp" #include "Encoders.hpp" -#include <armnn/Types.hpp> - -#include <armnnUtils/DataLayoutIndexed.hpp> - -#include <armnn/backends/Workload.hpp> -#include <armnn/backends/WorkloadData.hpp> +#include <armnn/Descriptors.hpp> namespace armnn { -void BatchToSpaceNd(const armnnUtils::DataLayoutIndexed& dataLayout, - const TensorInfo& inputTensorInfo, - const TensorInfo& outputTensorInfo, - const std::vector<unsigned int>& blockShape, - const std::vector<std::pair<unsigned int, unsigned int>>& cropsData, - Decoder<float>& inputDecoder, - Encoder<float>& outputEncoder); +void BatchToSpaceNd(const TensorInfo& inputInfo, + const TensorInfo& outputInfo, + const BatchToSpaceNdDescriptor& params, + Decoder<float>& inputData, + Encoder<float>& outputData); + } // namespace armnn diff --git a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp index 72c7a7687e..6bb8aff72c 100644 --- a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp +++ b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.cpp @@ -1,11 +1,11 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2018-2019,2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // -#include "BatchToSpaceNd.hpp" -#include "Profiling.hpp" #include "RefBatchToSpaceNdWorkload.hpp" +#include "BatchToSpaceNd.hpp" + #include "RefWorkloadUtils.hpp" namespace armnn @@ -32,8 +32,7 @@ void RefBatchToSpaceNdWorkload::Execute(std::vector<ITensorHandle*> inputs, std: std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(inputInfo, inputs[0]->Map()); std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(outputInfo, outputs[0]->Map()); - BatchToSpaceNd(m_Data.m_Parameters.m_DataLayout, inputInfo, outputInfo, m_Data.m_Parameters.m_BlockShape, - m_Data.m_Parameters.m_Crops, *inputDecoder, *outputEncoder); + BatchToSpaceNd(inputInfo, outputInfo, m_Data.m_Parameters, *inputDecoder, *outputEncoder); } diff --git a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp index ac6aad3eb2..5fb5835b68 100644 --- a/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp +++ b/src/backends/reference/workloads/RefBatchToSpaceNdWorkload.hpp @@ -1,14 +1,14 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2018-2019,2021-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "RefBaseWorkload.hpp" -#include <armnn/backends/WorkloadData.hpp> -namespace armnn { +namespace armnn +{ class RefBatchToSpaceNdWorkload : public RefBaseWorkload<BatchToSpaceNdQueueDescriptor> { diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp index 6aa422afdc..d29c2c801e 100644 --- a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp +++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2018-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -7,7 +7,6 @@ #include "SpaceToBatchNd.hpp" #include "RefWorkloadUtils.hpp" -#include <ResolveType.hpp> namespace armnn { @@ -28,12 +27,12 @@ void RefSpaceToBatchNdWorkload::Execute(std::vector<ITensorHandle*> inputs, std: ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefSpaceToBatchNdWorkload_Execute"); const TensorInfo& inputInfo = GetTensorInfo(inputs[0]); - std::unique_ptr<Decoder<float>> decoder = MakeDecoder<float>(inputInfo, inputs[0]->Map()); - const TensorInfo& outputInfo = GetTensorInfo(outputs[0]); - std::unique_ptr<Encoder<float>> encoder = MakeEncoder<float>(outputInfo, outputs[0]->Map()); - SpaceToBatchNd(inputInfo, outputInfo, m_Data.m_Parameters, *decoder, *encoder); + std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(inputInfo, inputs[0]->Map()); + std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(outputInfo, outputs[0]->Map()); + + SpaceToBatchNd(inputInfo, outputInfo, m_Data.m_Parameters, *inputDecoder, *outputEncoder); } } //namespace armnn diff --git a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp index f2c87682db..f9d75ee4d6 100644 --- a/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp +++ b/src/backends/reference/workloads/RefSpaceToBatchNdWorkload.hpp @@ -1,13 +1,11 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2018-2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include "RefBaseWorkload.hpp" -#include <armnn/TypesUtils.hpp> - namespace armnn { @@ -15,8 +13,10 @@ class RefSpaceToBatchNdWorkload : public RefBaseWorkload<SpaceToBatchNdQueueDesc { public: using RefBaseWorkload<SpaceToBatchNdQueueDescriptor>::RefBaseWorkload; + void Execute() const override; void ExecuteAsync(ExecutionData& executionData) override; + private: void Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const; }; diff --git a/src/backends/reference/workloads/SpaceToBatchNd.cpp b/src/backends/reference/workloads/SpaceToBatchNd.cpp index b6bab17367..c3f022c6a6 100644 --- a/src/backends/reference/workloads/SpaceToBatchNd.cpp +++ b/src/backends/reference/workloads/SpaceToBatchNd.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017-2019,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -19,15 +19,29 @@ unsigned int GetOffset(const TensorShape& shape, unsigned int c, const DataLayoutIndexed& dataLayout) { - if (dataLayout.GetDataLayout() == DataLayout::NHWC) + // 3D Tensors + unsigned int channelDimension3D = dataLayout.GetDataLayout() == DataLayout::NCHW ? 1 : 2; + if (shape.GetNumDimensions() == 3) { - return ((b * shape[dataLayout.GetHeightIndex()] + h) * shape[dataLayout.GetWidthIndex()] + w) * - shape[dataLayout.GetChannelsIndex()] + c; + return (b * shape[dataLayout.GetHeightIndex()] + h) * shape[channelDimension3D] + c; + } + // 4D Tensors + else if (shape.GetNumDimensions() == 4) + { + if (dataLayout.GetDataLayout() == DataLayout::NHWC) + { + return ((b * shape[dataLayout.GetHeightIndex()] + h) * shape[dataLayout.GetWidthIndex()] + w) * + shape[dataLayout.GetChannelsIndex()] + c; + } + else + { + return ((b * shape[dataLayout.GetChannelsIndex()] + c) * shape[dataLayout.GetHeightIndex()] + h) * + shape[dataLayout.GetWidthIndex()] + w; + } } else { - return ((b * shape[dataLayout.GetChannelsIndex()] + c) * shape[dataLayout.GetHeightIndex()] + h) * - shape[dataLayout.GetWidthIndex()] + w; + throw InvalidArgumentException("Tensor rank must be either 3 or 4", CHECK_LOCATION()); } } @@ -37,37 +51,46 @@ void SpaceToBatchNd(const TensorInfo& inputInfo, Decoder<float>& inputData, Encoder<float>& outputData) { + unsigned int rank = inputInfo.GetNumDimensions(); + if (rank != 3 && rank != 4 ) + { + throw InvalidArgumentException("Tensor rank must be either 3 or 4, but it is " + std::to_string(rank), + CHECK_LOCATION()); + } + DataLayoutIndexed dataLayout = params.m_DataLayout; + unsigned int channelDimension3D = params.m_DataLayout == DataLayout::NCHW ? 1 : 2; const TensorShape& inputShape = inputInfo.GetShape(); const TensorShape& outputShape = outputInfo.GetShape(); - const unsigned int channels = inputShape[dataLayout.GetChannelsIndex()]; + const unsigned int inputBatchSize = inputShape[0]; + const unsigned int outputBatchSize = outputShape[0]; - const unsigned int inputBatchSize = inputShape[0]; - const unsigned int inputHeight = inputShape[dataLayout.GetHeightIndex()]; - const unsigned int inputWidth = inputShape[dataLayout.GetWidthIndex()]; + const unsigned int channels = (rank == 3) ? inputShape[channelDimension3D] + : inputShape[dataLayout.GetChannelsIndex()]; - const unsigned int outputBatchSize = outputShape[0]; + const unsigned int inputHeight = inputShape[dataLayout.GetHeightIndex()]; + const unsigned int inputWidth = (rank == 3) ? 1 : inputShape[dataLayout.GetWidthIndex()]; const unsigned int outputHeight = outputShape[dataLayout.GetHeightIndex()]; - const unsigned int outputWidth = outputShape[dataLayout.GetWidthIndex()]; + const unsigned int outputWidth = (rank == 3) ? 1 : outputShape[dataLayout.GetWidthIndex()]; const unsigned int blockHeight = params.m_BlockShape[0]; - const unsigned int blockWidth = params.m_BlockShape[1]; + const unsigned int blockWidth = (rank == 3) ? 1 : params.m_BlockShape[1]; - const unsigned int paddingTop = params.m_PadList[0].first; - const unsigned int paddingLeft = params.m_PadList[1].first; + const unsigned int paddingTop = params.m_PadList[0].first; + const unsigned int paddingLeft = (rank == 3) ? 0 : params.m_PadList[1].first; - for (unsigned int outB = 0; outB < outputBatchSize; outB++) + for (unsigned int outB = 0; outB < outputBatchSize; ++outB) { unsigned int inB = outB % inputBatchSize; unsigned int shiftW = (outB / inputBatchSize) % blockWidth; unsigned int shiftH = (outB / inputBatchSize) / blockWidth; - for (unsigned int outH = 0; outH < outputHeight; outH++) + for (unsigned int outH = 0; outH < outputHeight; ++outH) { - for (unsigned int outW = 0; outW < outputWidth; outW++) + for (unsigned int outW = 0; outW < outputWidth; ++outW) { if (outH * blockHeight + shiftH < paddingTop || outH * blockHeight + shiftH >= paddingTop + inputHeight || @@ -117,10 +140,4 @@ void SpaceToBatchNd(const TensorInfo& inputInfo, } } -void SpaceToBatchNd(const TensorInfo& inputInfo, - const TensorInfo& outputInfo, - const SpaceToBatchNdDescriptor& params, - Decoder<float>& inputData, - Encoder<float>& outData); - } //namespace armnn diff --git a/src/backends/reference/workloads/SpaceToBatchNd.hpp b/src/backends/reference/workloads/SpaceToBatchNd.hpp index 57c9b6bc25..7de34ee59a 100644 --- a/src/backends/reference/workloads/SpaceToBatchNd.hpp +++ b/src/backends/reference/workloads/SpaceToBatchNd.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017-2019,2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -10,7 +10,6 @@ #include "Encoders.hpp" #include <armnn/Descriptors.hpp> -#include "armnn/Tensor.hpp" namespace armnn { |