diff options
Diffstat (limited to 'delegate')
| -rw-r--r-- | delegate/classic/src/BroadcastTo.hpp | 12 | ||||
| -rw-r--r-- | delegate/common/src/DelegateUtils.hpp | 15 | ||||
| -rw-r--r-- | delegate/common/src/test/DelegateUtilsTest.cpp | 54 | ||||
| -rw-r--r-- | delegate/opaque/src/BroadcastTo.hpp | 12 |
4 files changed, 91 insertions, 2 deletions
diff --git a/delegate/classic/src/BroadcastTo.hpp b/delegate/classic/src/BroadcastTo.hpp index 92aed79982..2e2b3ab155 100644 --- a/delegate/classic/src/BroadcastTo.hpp +++ b/delegate/classic/src/BroadcastTo.hpp @@ -1,11 +1,12 @@ // -// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2023-2024 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include <armnn/utility/IgnoreUnused.hpp> +#include <DelegateUtils.hpp> #include <tensorflow/lite/builtin_ops.h> #include <tensorflow/lite/c/builtin_op_data.h> @@ -83,6 +84,15 @@ namespace armnnDelegate const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + if (ZeroDimPresent({inputTensorInfo, outputTensorInfo})) + { + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: Zero dimension tensors are not supported in operator #%d node #%d: ", + broadcastToOperatorCode, nodeIndex); + return kTfLiteError; + } + auto* shapeData = tflite::GetTensorData<int32_t>(&tfLiteShapeTensor); auto shapeTensorNum = tfLiteShapeTensor.dims->data[0]; diff --git a/delegate/common/src/DelegateUtils.hpp b/delegate/common/src/DelegateUtils.hpp index 96767ff78c..245fc9be90 100644 --- a/delegate/common/src/DelegateUtils.hpp +++ b/delegate/common/src/DelegateUtils.hpp @@ -300,4 +300,19 @@ armnn::TensorInfo OutputShapeOfSqueeze(std::vector<uint32_t> squeezeDims, return outTensorInfo; } +bool ZeroDimPresent(std::initializer_list<armnn::TensorInfo> tensorInfoList) +{ + for (armnn::TensorInfo tensorInfo : tensorInfoList) + { + for (unsigned int i = 0; i < tensorInfo.GetNumDimensions(); ++i) + { + if (tensorInfo.GetShape()[i] == 0) + { + return true; + } + } + } + return false; +} + } // namespace anonymous diff --git a/delegate/common/src/test/DelegateUtilsTest.cpp b/delegate/common/src/test/DelegateUtilsTest.cpp new file mode 100644 index 0000000000..5ce470e289 --- /dev/null +++ b/delegate/common/src/test/DelegateUtilsTest.cpp @@ -0,0 +1,54 @@ +// +// Copyright © 2024 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include <armnn/Tensor.hpp> +#include <doctest/doctest.h> +#include <common/src/DelegateUtils.hpp> + +namespace armnn +{ + +TEST_SUITE("DelegateUtils_Tests") +{ + TEST_CASE("Zero_Dim_In_Input_Test_True") + { + unsigned int inputDimSizes[] = {0, 1, 2, 3}; + TensorInfo inputTensor = armnn::TensorInfo(4, inputDimSizes, DataType::Float32); + + CHECK(ZeroDimPresent({inputTensor}) == true); + } + + TEST_CASE("Zero_Dim_In_Input_Test_False") + { + unsigned int inputDimSizes[] = {1, 2, 3, 4}; + TensorInfo inputTensor = armnn::TensorInfo(4, inputDimSizes, DataType::Float32); + + CHECK(ZeroDimPresent({inputTensor}) == false); + } + + TEST_CASE("Zero_Dim_In_Output_Test_True") + { + unsigned int inputDimSizes[] = {1, 2, 3, 4}; + TensorInfo inputTensor = armnn::TensorInfo(4, inputDimSizes, DataType::Float32); + + unsigned int outputDimSizes[] = {0, 1, 2, 3}; + TensorInfo outputTensor = armnn::TensorInfo(4, outputDimSizes, DataType::Float32); + + CHECK(ZeroDimPresent({inputTensor, outputTensor}) == true); + } + + TEST_CASE("Zero_Dim_In_Output_Test_False") + { + unsigned int inputDimSizes[] = {1, 2, 3, 4}; + TensorInfo inputTensor = armnn::TensorInfo(4, inputDimSizes, DataType::Float32); + + unsigned int outputDimSizes[] = {1, 2, 3, 4}; + TensorInfo outputTensor = armnn::TensorInfo(4, outputDimSizes, DataType::Float32); + + CHECK(ZeroDimPresent({inputTensor, outputTensor}) == false); + } +} + +} // namespace armnn
\ No newline at end of file diff --git a/delegate/opaque/src/BroadcastTo.hpp b/delegate/opaque/src/BroadcastTo.hpp index 379587546f..8fcea9393c 100644 --- a/delegate/opaque/src/BroadcastTo.hpp +++ b/delegate/opaque/src/BroadcastTo.hpp @@ -1,11 +1,12 @@ // -// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2023-2024 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once #include <OpaqueDelegateUtils.hpp> +#include <DelegateUtils.hpp> namespace armnnOpaqueDelegate { @@ -102,6 +103,15 @@ namespace armnnOpaqueDelegate const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); + if (ZeroDimPresent({inputTensorInfo, outputTensorInfo})) + { + TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnOpaqueDelegate: Zero dimension tensors are not supported in operator #%d node #%d: ", + broadcastToOperatorCode, nodeIndex); + return kTfLiteError; + } + auto* shapeData = static_cast<int32_t*>(TfLiteOpaqueTensorData(tfLiteShapeTensor)); int32_t shapeTensorNum = TfLiteOpaqueTensorDim(tfLiteShapeTensor, 0); |