diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp | 312 |
1 files changed, 156 insertions, 156 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp index cc18dd4bb4..83f3528286 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2023 Arm Limited. + * Copyright (c) 2021, 2023-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -58,22 +58,22 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "2:" // Output channel loop: Load bias: Done "ldr q10, [%x[weights], #0x0]\n" "mov x22, %x[inptrs]\n" - "ldp x21, x20, [x22], #0x10\n" "lsr x23, %x[kernel_points], #0x1\n" - "ldr q3, [x21, #0x0]\n" - "ldr q2, [x21, #0x10]\n" "mov v16.16b, v31.16b\n" "mov v17.16b, v31.16b\n" - "ldr q1, [x20, #0x0]\n" - "ldr q0, [x20, #0x10]\n" "mov v18.16b, v31.16b\n" + "add %x[weights], %x[weights], #0x10\n" "mov v19.16b, v31.16b\n" "mov v20.16b, v31.16b\n" + "ldp x21, x20, [x22], #0x10\n" "mov v21.16b, v31.16b\n" - "add %x[weights], %x[weights], #0x10\n" "mov v22.16b, v31.16b\n" "mov v23.16b, v31.16b\n" "mov v24.16b, v31.16b\n" + "ldr q3, [x21, #0x0]\n" + "ldr q2, [x21, #0x10]\n" + "ldr q1, [x20, #0x0]\n" + "ldr q0, [x20, #0x10]\n" "mov v25.16b, v31.16b\n" "mov v26.16b, v31.16b\n" "mov v27.16b, v31.16b\n" @@ -98,9 +98,9 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "subs x23, x23, #0x1\n" "fmla v18.4s, v10.4s, v3.s[2]\n" "fmla v19.4s, v10.4s, v3.s[3]\n" - "ldr q3, [x21, #0x0]\n" "fmla v20.4s, v10.4s, v2.s[0]\n" "fmla v21.4s, v10.4s, v2.s[1]\n" + "ldr q3, [x21, #0x0]\n" "fmla v22.4s, v10.4s, v2.s[2]\n" "fmla v23.4s, v10.4s, v2.s[3]\n" "ldr q2, [x21, #0x10]\n" @@ -120,9 +120,9 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v17.4s, v9.4s, v8.s[1]\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x21, #0x0]\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" + "ldr q8, [x21, #0x0]\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" "ldr q7, [x21, #0x10]\n" @@ -168,71 +168,71 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v31.4s, v10.4s, v0.s[3]\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "fmin v16.4s, v16.4s, v11.4s\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "fmin v17.4s, v17.4s, v11.4s\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" - "fmin v18.4s, v18.4s, v11.4s\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" - "fmin v19.4s, v19.4s, v11.4s\n" "fmla v24.4s, v9.4s, v6.s[0]\n" "fmla v25.4s, v9.4s, v6.s[1]\n" - "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v16.4s, v16.4s, v11.4s\n" "fmla v26.4s, v9.4s, v6.s[2]\n" "fmla v27.4s, v9.4s, v6.s[3]\n" - "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v17.4s, v17.4s, v11.4s\n" "fmla v28.4s, v9.4s, v5.s[0]\n" "fmla v29.4s, v9.4s, v5.s[1]\n" - "fmin v22.4s, v22.4s, v11.4s\n" + "fmin v18.4s, v18.4s, v11.4s\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v22.4s, v22.4s, v11.4s\n" "fmin v23.4s, v23.4s, v11.4s\n" "fmax v16.4s, v16.4s, v12.4s\n" "fmax v17.4s, v17.4s, v12.4s\n" - "str q16, [x27, x28]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "fmax v18.4s, v18.4s, v12.4s\n" "fmax v19.4s, v19.4s, v12.4s\n" - "str q17, [x26, x28]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "fmax v20.4s, v20.4s, v12.4s\n" "fmax v21.4s, v21.4s, v12.4s\n" - "str q18, [x25, x28]\n" - "ldr x25, [%x[outptrs], #0x50]\n" "fmax v22.4s, v22.4s, v12.4s\n" "fmax v23.4s, v23.4s, v12.4s\n" - "str q19, [x24, x28]\n" - "ldr x24, [%x[outptrs], #0x58]\n" + "str q16, [x27, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "fmin v24.4s, v24.4s, v11.4s\n" "fmin v25.4s, v25.4s, v11.4s\n" - "str q20, [x23, x28]\n" - "ldr x23, [%x[outptrs], #0x60]\n" + "str q17, [x26, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "fmin v26.4s, v26.4s, v11.4s\n" "fmin v27.4s, v27.4s, v11.4s\n" - "str q21, [x22, x28]\n" - "ldr x22, [%x[outptrs], #0x68]\n" + "str q18, [x25, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "fmin v28.4s, v28.4s, v11.4s\n" "fmin v29.4s, v29.4s, v11.4s\n" - "str q22, [x21, x28]\n" - "ldr x21, [%x[outptrs], #0x70]\n" + "str q19, [x24, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "fmin v30.4s, v30.4s, v11.4s\n" "fmin v31.4s, v31.4s, v11.4s\n" - "str q23, [x20, x28]\n" - "ldr x20, [%x[outptrs], #0x78]\n" + "str q20, [x23, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "str q21, [x22, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "fmax v24.4s, v24.4s, v12.4s\n" "fmax v25.4s, v25.4s, v12.4s\n" - "str q24, [x27, x28]\n" + "str q22, [x21, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "fmax v26.4s, v26.4s, v12.4s\n" "fmax v27.4s, v27.4s, v12.4s\n" - "str q25, [x26, x28]\n" + "str q23, [x20, x28]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "fmax v28.4s, v28.4s, v12.4s\n" "fmax v29.4s, v29.4s, v12.4s\n" - "str q26, [x25, x28]\n" "fmax v30.4s, v30.4s, v12.4s\n" "fmax v31.4s, v31.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "str q25, [x26, x28]\n" + "str q26, [x25, x28]\n" "str q27, [x24, x28]\n" "str q28, [x23, x28]\n" "str q29, [x22, x28]\n" @@ -246,16 +246,16 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "lsl x28, x10, #0x2\n" "fmla v18.4s, v10.4s, v3.s[2]\n" "fmla v19.4s, v10.4s, v3.s[3]\n" - "ldr q4, [x20, #0x0]\n" "ldr x27, [%x[outptrs], #0x0]\n" + "ldr x26, [%x[outptrs], #0x8]\n" "fmla v20.4s, v10.4s, v2.s[0]\n" "fmla v21.4s, v10.4s, v2.s[1]\n" - "ldr x26, [%x[outptrs], #0x8]\n" "ldr x25, [%x[outptrs], #0x10]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "ldr q4, [x20, #0x0]\n" "fmla v22.4s, v10.4s, v2.s[2]\n" "fmla v23.4s, v10.4s, v2.s[3]\n" "ldr q3, [x20, #0x10]\n" - "ldr x24, [%x[outptrs], #0x18]\n" "fmla v24.4s, v10.4s, v1.s[0]\n" "fmla v25.4s, v10.4s, v1.s[1]\n" "ldr x23, [%x[outptrs], #0x20]\n" @@ -290,71 +290,71 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v31.4s, v9.4s, v5.s[3]\n" "fmla v16.4s, v1.4s, v4.s[0]\n" "fmla v17.4s, v1.4s, v4.s[1]\n" - "fmin v16.4s, v16.4s, v11.4s\n" "fmla v18.4s, v1.4s, v4.s[2]\n" "fmla v19.4s, v1.4s, v4.s[3]\n" - "fmin v17.4s, v17.4s, v11.4s\n" "fmla v20.4s, v1.4s, v3.s[0]\n" "fmla v21.4s, v1.4s, v3.s[1]\n" - "fmin v18.4s, v18.4s, v11.4s\n" "fmla v22.4s, v1.4s, v3.s[2]\n" "fmla v23.4s, v1.4s, v3.s[3]\n" - "fmin v19.4s, v19.4s, v11.4s\n" "fmla v24.4s, v1.4s, v2.s[0]\n" "fmla v25.4s, v1.4s, v2.s[1]\n" - "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v16.4s, v16.4s, v11.4s\n" "fmla v26.4s, v1.4s, v2.s[2]\n" "fmla v27.4s, v1.4s, v2.s[3]\n" - "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v17.4s, v17.4s, v11.4s\n" "fmla v28.4s, v1.4s, v0.s[0]\n" "fmla v29.4s, v1.4s, v0.s[1]\n" - "fmin v22.4s, v22.4s, v11.4s\n" + "fmin v18.4s, v18.4s, v11.4s\n" "fmla v30.4s, v1.4s, v0.s[2]\n" "fmla v31.4s, v1.4s, v0.s[3]\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v22.4s, v22.4s, v11.4s\n" "fmin v23.4s, v23.4s, v11.4s\n" "fmax v16.4s, v16.4s, v12.4s\n" "fmax v17.4s, v17.4s, v12.4s\n" - "str q16, [x27, x28]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "fmax v18.4s, v18.4s, v12.4s\n" "fmax v19.4s, v19.4s, v12.4s\n" - "str q17, [x26, x28]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "fmax v20.4s, v20.4s, v12.4s\n" "fmax v21.4s, v21.4s, v12.4s\n" - "str q18, [x25, x28]\n" - "ldr x25, [%x[outptrs], #0x50]\n" "fmax v22.4s, v22.4s, v12.4s\n" "fmax v23.4s, v23.4s, v12.4s\n" - "str q19, [x24, x28]\n" - "ldr x24, [%x[outptrs], #0x58]\n" + "str q16, [x27, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "fmin v24.4s, v24.4s, v11.4s\n" "fmin v25.4s, v25.4s, v11.4s\n" - "str q20, [x23, x28]\n" - "ldr x23, [%x[outptrs], #0x60]\n" + "str q17, [x26, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "fmin v26.4s, v26.4s, v11.4s\n" "fmin v27.4s, v27.4s, v11.4s\n" - "str q21, [x22, x28]\n" - "ldr x22, [%x[outptrs], #0x68]\n" + "str q18, [x25, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "fmin v28.4s, v28.4s, v11.4s\n" "fmin v29.4s, v29.4s, v11.4s\n" - "str q22, [x21, x28]\n" - "ldr x21, [%x[outptrs], #0x70]\n" + "str q19, [x24, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "fmin v30.4s, v30.4s, v11.4s\n" "fmin v31.4s, v31.4s, v11.4s\n" - "str q23, [x20, x28]\n" - "ldr x20, [%x[outptrs], #0x78]\n" + "str q20, [x23, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "str q21, [x22, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "fmax v24.4s, v24.4s, v12.4s\n" "fmax v25.4s, v25.4s, v12.4s\n" - "str q24, [x27, x28]\n" + "str q22, [x21, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "fmax v26.4s, v26.4s, v12.4s\n" "fmax v27.4s, v27.4s, v12.4s\n" - "str q25, [x26, x28]\n" + "str q23, [x20, x28]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "fmax v28.4s, v28.4s, v12.4s\n" "fmax v29.4s, v29.4s, v12.4s\n" - "str q26, [x25, x28]\n" "fmax v30.4s, v30.4s, v12.4s\n" "fmax v31.4s, v31.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "str q25, [x26, x28]\n" + "str q26, [x25, x28]\n" "str q27, [x24, x28]\n" "str q28, [x23, x28]\n" "str q29, [x22, x28]\n" @@ -364,80 +364,80 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "6:" // Output channel loop: Single kernel point "fmla v16.4s, v10.4s, v3.s[0]\n" "fmla v17.4s, v10.4s, v3.s[1]\n" - "fmin v16.4s, v16.4s, v11.4s\n" "lsl x28, x10, #0x2\n" + "ldr x27, [%x[outptrs], #0x0]\n" "fmla v18.4s, v10.4s, v3.s[2]\n" "fmla v19.4s, v10.4s, v3.s[3]\n" - "fmin v17.4s, v17.4s, v11.4s\n" - "ldr x27, [%x[outptrs], #0x0]\n" + "ldr x26, [%x[outptrs], #0x8]\n" + "ldr x25, [%x[outptrs], #0x10]\n" "fmla v20.4s, v10.4s, v2.s[0]\n" "fmla v21.4s, v10.4s, v2.s[1]\n" - "fmin v18.4s, v18.4s, v11.4s\n" - "ldr x26, [%x[outptrs], #0x8]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "ldr x23, [%x[outptrs], #0x20]\n" "fmla v22.4s, v10.4s, v2.s[2]\n" "fmla v23.4s, v10.4s, v2.s[3]\n" - "fmin v19.4s, v19.4s, v11.4s\n" - "ldr x25, [%x[outptrs], #0x10]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "ldr x21, [%x[outptrs], #0x30]\n" "fmla v24.4s, v10.4s, v1.s[0]\n" "fmla v25.4s, v10.4s, v1.s[1]\n" - "fmin v20.4s, v20.4s, v11.4s\n" - "ldr x24, [%x[outptrs], #0x18]\n" + "fmin v16.4s, v16.4s, v11.4s\n" + "ldr x20, [%x[outptrs], #0x38]\n" "fmla v26.4s, v10.4s, v1.s[2]\n" "fmla v27.4s, v10.4s, v1.s[3]\n" - "fmin v21.4s, v21.4s, v11.4s\n" - "ldr x23, [%x[outptrs], #0x20]\n" + "fmin v17.4s, v17.4s, v11.4s\n" "fmla v28.4s, v10.4s, v0.s[0]\n" "fmla v29.4s, v10.4s, v0.s[1]\n" - "fmin v22.4s, v22.4s, v11.4s\n" - "ldr x22, [%x[outptrs], #0x28]\n" + "fmin v18.4s, v18.4s, v11.4s\n" "fmla v30.4s, v10.4s, v0.s[2]\n" "fmla v31.4s, v10.4s, v0.s[3]\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v22.4s, v22.4s, v11.4s\n" "fmin v23.4s, v23.4s, v11.4s\n" - "ldr x21, [%x[outptrs], #0x30]\n" - "ldr x20, [%x[outptrs], #0x38]\n" "fmax v16.4s, v16.4s, v12.4s\n" "fmax v17.4s, v17.4s, v12.4s\n" - "str q16, [x27, x28]\n" "fmax v18.4s, v18.4s, v12.4s\n" "fmax v19.4s, v19.4s, v12.4s\n" - "str q17, [x26, x28]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "fmax v20.4s, v20.4s, v12.4s\n" "fmax v21.4s, v21.4s, v12.4s\n" - "str q18, [x25, x28]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "fmax v22.4s, v22.4s, v12.4s\n" "fmax v23.4s, v23.4s, v12.4s\n" - "str q19, [x24, x28]\n" - "ldr x25, [%x[outptrs], #0x50]\n" + "str q16, [x27, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "fmin v24.4s, v24.4s, v11.4s\n" "fmin v25.4s, v25.4s, v11.4s\n" - "str q20, [x23, x28]\n" - "ldr x24, [%x[outptrs], #0x58]\n" + "str q17, [x26, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "fmin v26.4s, v26.4s, v11.4s\n" "fmin v27.4s, v27.4s, v11.4s\n" - "str q21, [x22, x28]\n" - "ldr x23, [%x[outptrs], #0x60]\n" + "str q18, [x25, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "fmin v28.4s, v28.4s, v11.4s\n" "fmin v29.4s, v29.4s, v11.4s\n" - "str q22, [x21, x28]\n" - "ldr x22, [%x[outptrs], #0x68]\n" + "str q19, [x24, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "fmin v30.4s, v30.4s, v11.4s\n" "fmin v31.4s, v31.4s, v11.4s\n" - "str q23, [x20, x28]\n" - "ldr x21, [%x[outptrs], #0x70]\n" - "ldr x20, [%x[outptrs], #0x78]\n" + "str q20, [x23, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "str q21, [x22, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "fmax v24.4s, v24.4s, v12.4s\n" "fmax v25.4s, v25.4s, v12.4s\n" - "str q24, [x27, x28]\n" + "str q22, [x21, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "fmax v26.4s, v26.4s, v12.4s\n" "fmax v27.4s, v27.4s, v12.4s\n" - "str q25, [x26, x28]\n" + "str q23, [x20, x28]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "fmax v28.4s, v28.4s, v12.4s\n" "fmax v29.4s, v29.4s, v12.4s\n" - "str q26, [x25, x28]\n" "fmax v30.4s, v30.4s, v12.4s\n" "fmax v31.4s, v31.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "str q25, [x26, x28]\n" + "str q26, [x25, x28]\n" "str q27, [x24, x28]\n" "str q28, [x23, x28]\n" "str q29, [x22, x28]\n" @@ -464,22 +464,22 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "11:" // Output channel oddments: Load bias: Done "ldr q10, [%x[weights], #0x0]\n" "mov x22, %x[inptrs]\n" - "ldp x21, x20, [x22], #0x10\n" "lsr x23, %x[kernel_points], #0x1\n" - "ldr q3, [x21, #0x0]\n" - "ldr q2, [x21, #0x10]\n" "mov v16.16b, v31.16b\n" "mov v17.16b, v31.16b\n" - "ldr q1, [x20, #0x0]\n" - "ldr q0, [x20, #0x10]\n" "mov v18.16b, v31.16b\n" + "add %x[weights], %x[weights], #0x10\n" "mov v19.16b, v31.16b\n" "mov v20.16b, v31.16b\n" + "ldp x21, x20, [x22], #0x10\n" "mov v21.16b, v31.16b\n" - "add %x[weights], %x[weights], #0x10\n" "mov v22.16b, v31.16b\n" "mov v23.16b, v31.16b\n" "mov v24.16b, v31.16b\n" + "ldr q3, [x21, #0x0]\n" + "ldr q2, [x21, #0x10]\n" + "ldr q1, [x20, #0x0]\n" + "ldr q0, [x20, #0x10]\n" "mov v25.16b, v31.16b\n" "mov v26.16b, v31.16b\n" "mov v27.16b, v31.16b\n" @@ -504,9 +504,9 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "subs x23, x23, #0x1\n" "fmla v18.4s, v10.4s, v3.s[2]\n" "fmla v19.4s, v10.4s, v3.s[3]\n" - "ldr q3, [x21, #0x0]\n" "fmla v20.4s, v10.4s, v2.s[0]\n" "fmla v21.4s, v10.4s, v2.s[1]\n" + "ldr q3, [x21, #0x0]\n" "fmla v22.4s, v10.4s, v2.s[2]\n" "fmla v23.4s, v10.4s, v2.s[3]\n" "ldr q2, [x21, #0x10]\n" @@ -526,9 +526,9 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v17.4s, v9.4s, v8.s[1]\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x21, #0x0]\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" + "ldr q8, [x21, #0x0]\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" "ldr q7, [x21, #0x10]\n" @@ -586,9 +586,9 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "ldp x21, x20, [x22], #0x10\n" "fmla v18.4s, v10.4s, v3.s[2]\n" "fmla v19.4s, v10.4s, v3.s[3]\n" - "ldr q4, [x21, #0x0]\n" "fmla v20.4s, v10.4s, v2.s[0]\n" "fmla v21.4s, v10.4s, v2.s[1]\n" + "ldr q4, [x21, #0x0]\n" "fmla v22.4s, v10.4s, v2.s[2]\n" "fmla v23.4s, v10.4s, v2.s[3]\n" "ldr q3, [x21, #0x10]\n" @@ -690,47 +690,47 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "tbz %x[n_output_channels], #1, 17f\n" "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" - "add x27, x27, x10, LSL #2\n" - "add x26, x26, x10, LSL #2\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" - "add x25, x25, x10, LSL #2\n" - "add x24, x24, x10, LSL #2\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" - "add x23, x23, x10, LSL #2\n" - "add x22, x22, x10, LSL #2\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x21, x21, x10, LSL #2\n" - "add x20, x20, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v16.d }[0], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x27, x27, x10, LSL #2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v17.d }[0], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x26, x26, x10, LSL #2\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" "st1 { v18.d }[0], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" - "add x25, x25, x10, LSL #2\n" "st1 { v19.d }[0], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x24, x24, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" "st1 { v20.d }[0], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x23, x23, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" "st1 { v21.d }[0], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x22, x22, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" "st1 { v22.d }[0], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x21, x21, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v23.d }[0], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x20, x20, x10, LSL #2\n" - "add x10, x10, #0x2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v24.d }[0], [x27]\n" + "add x21, x21, x10, LSL #2\n" "st1 { v25.d }[0], [x26]\n" + "add x20, x20, x10, LSL #2\n" + "add x10, x10, #0x2\n" "st1 { v26.d }[0], [x25]\n" "st1 { v27.d }[0], [x24]\n" "st1 { v28.d }[0], [x23]\n" @@ -740,46 +740,46 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "tbz %x[n_output_channels], #0, 18f\n" "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" - "add x27, x27, x10, LSL #2\n" - "add x26, x26, x10, LSL #2\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" - "add x25, x25, x10, LSL #2\n" - "add x24, x24, x10, LSL #2\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" - "add x23, x23, x10, LSL #2\n" - "add x22, x22, x10, LSL #2\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x21, x21, x10, LSL #2\n" - "add x20, x20, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v16.s }[2], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x27, x27, x10, LSL #2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v17.s }[2], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x26, x26, x10, LSL #2\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" "st1 { v18.s }[2], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" - "add x25, x25, x10, LSL #2\n" "st1 { v19.s }[2], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x24, x24, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" "st1 { v20.s }[2], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x23, x23, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" "st1 { v21.s }[2], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x22, x22, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" "st1 { v22.s }[2], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x21, x21, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v23.s }[2], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x20, x20, x10, LSL #2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v24.s }[2], [x27]\n" + "add x21, x21, x10, LSL #2\n" "st1 { v25.s }[2], [x26]\n" + "add x20, x20, x10, LSL #2\n" "st1 { v26.s }[2], [x25]\n" "st1 { v27.s }[2], [x24]\n" "st1 { v28.s }[2], [x23]\n" @@ -790,46 +790,46 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "17:" // Output channel oddments: Done: Store: Bit 1: Unset "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" - "add x27, x27, x10, LSL #2\n" - "add x26, x26, x10, LSL #2\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" - "add x25, x25, x10, LSL #2\n" - "add x24, x24, x10, LSL #2\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" - "add x23, x23, x10, LSL #2\n" - "add x22, x22, x10, LSL #2\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x21, x21, x10, LSL #2\n" - "add x20, x20, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v16.s }[0], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x27, x27, x10, LSL #2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v17.s }[0], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x26, x26, x10, LSL #2\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" "st1 { v18.s }[0], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" - "add x25, x25, x10, LSL #2\n" "st1 { v19.s }[0], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x24, x24, x10, LSL #2\n" + "add x27, x27, x10, LSL #2\n" "st1 { v20.s }[0], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x23, x23, x10, LSL #2\n" + "add x26, x26, x10, LSL #2\n" "st1 { v21.s }[0], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x22, x22, x10, LSL #2\n" + "add x25, x25, x10, LSL #2\n" "st1 { v22.s }[0], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x21, x21, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" "st1 { v23.s }[0], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x20, x20, x10, LSL #2\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" "st1 { v24.s }[0], [x27]\n" + "add x21, x21, x10, LSL #2\n" "st1 { v25.s }[0], [x26]\n" + "add x20, x20, x10, LSL #2\n" "st1 { v26.s }[0], [x25]\n" "st1 { v27.s }[0], [x24]\n" "st1 { v28.s }[0], [x23]\n" |