diff options
Diffstat (limited to 'src/mlia/resources/vela/vela.ini')
| -rw-r--r-- | src/mlia/resources/vela/vela.ini | 51 |
1 files changed, 48 insertions, 3 deletions
diff --git a/src/mlia/resources/vela/vela.ini b/src/mlia/resources/vela/vela.ini index 29a5179..747dc3d 100644 --- a/src/mlia/resources/vela/vela.ini +++ b/src/mlia/resources/vela/vela.ini @@ -1,4 +1,4 @@ -; SPDX-FileCopyrightText: Copyright 2020, 2022, Arm Limited and/or its affiliates. +; SPDX-FileCopyrightText: Copyright 2020, 2022, 2024, Arm Limited and/or its affiliates. ; SPDX-License-Identifier: Apache-2.0 ; ----------------------------------------------------------------------------- @@ -6,6 +6,19 @@ ; ----------------------------------------------------------------------------- ; System Configuration +; Ethos-U55 Deep Embedded: SRAM (1.6 GB/s) and Flash (0.1 GB/s) +[System_Config.Ethos_U55_Deep_Embedded] +core_clock=200e6 +axi0_port=Sram +axi1_port=OffChipFlash +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +OffChipFlash_clock_scale=0.0625 +OffChipFlash_burst_length=128 +OffChipFlash_read_latency=64 +OffChipFlash_write_latency=64 ; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s) [System_Config.Ethos_U55_High_End_Embedded] @@ -35,6 +48,20 @@ OffChipFlash_burst_length=128 OffChipFlash_read_latency=64 OffChipFlash_write_latency=64 +; Ethos-U65 Mid-End: SRAM (8 GB/s) and DRAM (3.75 GB/s) +[System_Config.Ethos_U65_Mid_End] +core_clock=500e6 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.46875 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + ; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s) [System_Config.Ethos_U65_High_End] core_clock=1e9 @@ -49,6 +76,20 @@ Dram_burst_length=128 Dram_read_latency=500 Dram_write_latency=250 +; Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s) +[System_Config.Ethos_U65_Client_Server] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + ; ----------------------------------------------------------------------------- ; Memory Mode @@ -58,7 +99,6 @@ Dram_write_latency=250 const_mem_area=Axi0 arena_mem_area=Axi0 cache_mem_area=Axi0 -arena_cache_size=2096768 ; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software ; The non-SRAM memory is assumed to be read-only @@ -66,7 +106,6 @@ arena_cache_size=2096768 const_mem_area=Axi1 arena_mem_area=Axi0 cache_mem_area=Axi0 -arena_cache_size=2096768 ; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U ; The non-SRAM memory is assumed to be read-writeable @@ -75,3 +114,9 @@ const_mem_area=Axi1 arena_mem_area=Axi1 cache_mem_area=Axi0 arena_cache_size=393216 + +; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U +; The non-SRAM memory is assumed to be read-writeable +[Memory_Mode.Dedicated_Sram_512KB] +inherit=Memory_Mode.Dedicated_Sram +arena_cache_size=524288 |