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-rw-r--r--source/hal/source/platform/mps3/CMakeLists.txt29
-rw-r--r--source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h12
-rw-r--r--source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h15
-rw-r--r--source/hal/source/platform/mps3/source/platform_drivers.c14
-rw-r--r--source/hal/source/platform/simple/include/peripheral_memmap.h24
-rw-r--r--source/hal/source/platform/simple/source/platform_drivers.c12
6 files changed, 34 insertions, 72 deletions
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt
index 5008f0b..4f77bdd 100644
--- a/source/hal/source/platform/mps3/CMakeLists.txt
+++ b/source/hal/source/platform/mps3/CMakeLists.txt
@@ -1,5 +1,6 @@
#----------------------------------------------------------------------------
-# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its
+# affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -36,15 +37,23 @@ if (TARGET_SUBSYSTEM STREQUAL sse-300)
set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate")
set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)")
set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address")
- set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address")
set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U55 Interrupt")
set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable")
set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable")
- if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
- set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0")
- set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1")
- endif()
+ if (ETHOS_U_SEC_ENABLED)
+ set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address")
+ if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0")
+ set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1")
+ endif()
+ else ()
+ set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address")
+ if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ set(TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter 0")
+ set(TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter 1")
+ endif()
+ endif ()
endif()
# Define target specific base addresses here (before adding the components)
@@ -53,11 +62,17 @@ if (TARGET_SUBSYSTEM STREQUAL sse-310)
set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate")
set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)")
set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address")
- set(ETHOS_U_BASE_ADDR "0x50004000" CACHE STRING "Ethos-U NPU base address")
+
set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U55 Interrupt")
set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable")
set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable")
+ if (ETHOS_U_SEC_ENABLED)
+ set(ETHOS_U_BASE_ADDR "0x50004000" CACHE STRING "Ethos-U NPU base address")
+ else ()
+ set(ETHOS_U_BASE_ADDR "0x40004000" CACHE STRING "Ethos-U NPU base address")
+ endif ()
+
if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
message(FATAL_ERROR "Timing adapter support should be disabled for ${TARGET_SUBSYSTEM}")
endif()
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
index 85c7a8e..fd3ed15 100644
--- a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
+++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
@@ -1,6 +1,6 @@
/*
- * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -65,10 +65,6 @@
#define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */
#define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/
-#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/
-#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
-
#define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/
#define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */
/* #undef HDMI_AUDIO_BASE */
@@ -138,10 +134,6 @@
#define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC9220 Base Address */
#define SEC_USB_BASE (0x51500000) /* USB Base Address */
-#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/
-#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
-
/* #undef SEC_USER_BASE */
#define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */
diff --git a/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h
index eeaca69..3c7c031 100644
--- a/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h
+++ b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h
@@ -1,6 +1,6 @@
/*
- * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -65,10 +65,6 @@
#define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */
#define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/
-#define ETHOS_U_NPU_BASE (0x40004000) /* Ethos-U NPU base address*/
-#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
-
#define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/
#define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */
/* #undef HDMI_AUDIO_BASE */
@@ -136,16 +132,9 @@
#define SEC_CLCD_CONFIG_BASE (0x5930A000) /* CLCD CONFIG Base Address */
#define SEC_RTC_BASE (0x5930B000) /* RTC Base address */
-
-
-
#define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC91C111 Base Address */
#define SEC_USB_BASE (0x51500000) /* USB Base Address */
-#define SEC_ETHOS_U_NPU_BASE (0x50004000) /* Ethos-U NPU base address*/
-#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
-
/* #undef SEC_USER_BASE */
#define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
index 73b388b..1890e3b 100644
--- a/source/hal/source/platform/mps3/source/platform_drivers.c
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -1,6 +1,6 @@
/*
- * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: Copyright 2022-2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -21,8 +21,6 @@
#include "uart_stdout.h" /* stdout over UART. */
#include "smm_mps3.h" /* Memory map for MPS3. */
-#include <string.h> /* For strncpy */
-
#if defined(ARM_NPU)
#include "ethosu_npu_init.h"
@@ -30,14 +28,6 @@
#include "ethosu_ta_init.h"
#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
-#if defined(ETHOS_U_BASE_ADDR)
- #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR)
- #error "NPU component configured with incorrect NPU base address."
- #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */
-#else
- #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component."
-#endif /* defined(ETHOS_U_BASE_ADDR) */
-
#endif /* ARM_NPU */
/**
diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h
index 761fad9..e302e30 100644
--- a/source/hal/source/platform/simple/include/peripheral_memmap.h
+++ b/source/hal/source/platform/simple/include/peripheral_memmap.h
@@ -1,6 +1,6 @@
/*
- * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -18,23 +18,7 @@
#ifndef PERIPHERAL_MEMMAP_H
#define PERIPHERAL_MEMMAP_H
-#define DESIGN_NAME "Simple platform"
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */
-
-#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/
-#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
-
-/******************************************************************************/
-/* Secure Peripheral memory map */
-/******************************************************************************/
-
-#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/
-#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
-#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
+#define DESIGN_NAME "Simple platform"
+#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */
#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/source/platform_drivers.c b/source/hal/source/platform/simple/source/platform_drivers.c
index 914b1ac..af854d7 100644
--- a/source/hal/source/platform/simple/source/platform_drivers.c
+++ b/source/hal/source/platform/simple/source/platform_drivers.c
@@ -1,6 +1,6 @@
/*
- * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -30,14 +30,6 @@
#include "ethosu_ta_init.h"
#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
-#if defined(ETHOS_U_BASE_ADDR)
- #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR)
- #error "NPU component configured with incorrect NPU base address."
- #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */
-#else
- #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component."
-#endif /* defined(ETHOS_U_BASE_ADDR) */
-
#endif /* ARM_NPU */
/* Platform name */