diff options
| author | alexander <alexander.efremov@arm.com> | 2022-02-10 16:15:54 +0000 |
|---|---|---|
| committer | alexander <alexander.efremov@arm.com> | 2022-02-10 18:04:42 +0000 |
| commit | 31ae9f09bb3535975595e999fbc7baca889e46e8 (patch) | |
| tree | 71f0cadc2620b9d18e474e5d40eda7b3d30a8ce4 /source | |
| parent | 3107aa2152de9be8317e62da1d0327bcad6552e2 (diff) | |
| download | ml-embedded-evaluation-kit-31ae9f09bb3535975595e999fbc7baca889e46e8.tar.gz | |
MLECO-2682: CMake and source refactoring.
MLECO-2930: logging macros were extracted from hal.h and used separately around the code.
MLECO-2931: arm_math lib introduced, cmsis-dsp removed from top level linkage.
MLECO-2915: platform related post-build steps.
Change-Id: Id718884e22f262a5c070ded3f3f5d4b048820147
Signed-off-by: alexander <alexander.efremov@arm.com>
Diffstat (limited to 'source')
123 files changed, 2001 insertions, 1224 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld deleted file mode 100644 index d369fa7..0000000 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -__STACK_SIZE = 0x00060000; -__HEAP_SIZE = 0x000C0000; - -/* System memory brief */ -MEMORY -{ - ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 - BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 - SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 - DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 - - /* Dynamic load regions declared for use by FVP only - * These regions are mentioned in the CMake subsystem profile. - * Do not change the addresses here in isolation. */ - DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000 - DDR_dynamic_ifm (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000 - DDR_dynamic_ofm (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text.at_itcm : - { - KEEP(*(.vectors)) - - /** - * All code goes here, with one exception of - * all_ops_resolver object file. This code - * instead placed on BRAM. See comment in the - * BRAM section for details. - **/ - *(EXCLUDE_FILE(*all_ops_resolver.o *hal.c.obj) .text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - KEEP(*(.eh_frame*)) - } > ITCM - - __exidx_start = .; - .ARM.exidx.at_itcm : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .zero.table.at_itcm : - { - . = ALIGN(4); - __zero_table_start__ = .; - - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ - - __zero_table_end__ = .; - } > ITCM - - .copy.table.at_itcm : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Section to be copied - part 1: any data to be placed in BRAM */ - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */ - - /* Section to be copied - part 2: RO data for for DTCM */ - LONG (__etext2) - LONG (__ro_data_start__) - LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */ - - __copy_table_end__ = .; - } > ITCM - - __itcm_total = ALIGN(4); - - ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow") - - .sram : - { - . = ALIGN(16); - /* Cache area (if used) */ - *(.bss.NoInit.ethos_u_cache) - . = ALIGN (16); - /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ - *(.bss.NoInit.activation_buf_sram) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - ASSERT( - (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM), - "DTCM overflow") - - .ddr.at_ddr : - { - /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. - * Force the alignment here as a workaround */ - . = ALIGN(16); - /* nn model's baked in input matrices */ - *(ifm) - . = ALIGN(16); - /* nn model's default space */ - *(nn_model) - . = ALIGN (16); - /* labels */ - *(labels) - . = ALIGN (16); - /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ - *(activation_buf_dram) - . = ALIGN (16); - } > DDR AT > DDR - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .bram.at_ddr : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - KEEP(*(.jcr*)) - . = ALIGN(4); - - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - - /** - * Place the all ops resolver code data here. This accounts - * for ~4k worth of saving on the ITCM load region. It is - * only designed to be included (by default) for the inference - * runner use case. - **/ - *all_ops_resolver.o (*.text*) - . = ALIGN(4); - *hal.c.obj (*.text*) - . = ALIGN(4); - - __data_end__ = .; - } > BRAM - - __etext2 = __etext + (__data_end__ - __data_start__); - - .data.at_ddr : AT (__etext2) - { - . = ALIGN(4); - __ro_data_start__ = .; - - *(.rodata*) - . = ALIGN(4); - * (npu_driver_version) - . = ALIGN(4); - * (npu_driver_arch_version) - . = ALIGN(4); - - __ro_data_end__ = .; - } > BRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > BRAM - - ASSERT ( - (__ro_data_end__ - __ro_data_start__) - + (__data_end__ - __data_start__) - + __HEAP_SIZE <= LENGTH(BRAM), - "BRAM overflow") -} diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct deleted file mode 100644 index f78dc25..0000000 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct +++ /dev/null @@ -1,145 +0,0 @@ -; Copyright (c) 2021 Arm Limited. All rights reserved. -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -; ************************************************************* -; *** Scatter-Loading Description File *** -; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping information. -; -; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and -; the model should only be placed in those regions. -; -;--------------------------------------------------------- -; First load region (ITCM) -;--------------------------------------------------------- -LOAD_REGION_0 0x00000000 0x00080000 -{ - ;----------------------------------------------------- - ; First part of code mem - 512kiB - ;----------------------------------------------------- - itcm.bin 0x00000000 0x00080000 - { - *.o (RESET, +First) - * (InRoot$$Sections) - - ; Essentially only RO-CODE, RO-DATA is in a - ; different region. - .ANY (+RO) - } - - ;----------------------------------------------------- - ; 128kiB of 512kiB DTCM is used for any other RW or ZI - ; data. Note: this region is internal to the Cortex-M - ; CPU. - ;----------------------------------------------------- - dtcm.bin 0x20000000 0x00020000 - { - ; Any R/W and/or zero initialised data - .ANY(+RW +ZI) - } - - ;----------------------------------------------------- - ; 384kiB of stack space within the DTCM region. See - ; `dtcm.bin` for the first section. Note: by virtue of - ; being part of DTCM, this region is only accessible - ; from Cortex-M55. - ;----------------------------------------------------- - ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 - {} - - ;----------------------------------------------------- - ; FPGA internal SRAM of 2MiB - reserved for activation - ; buffers. - ; This region should have 3 cycle read latency from - ; both Cortex-M55 and Ethos-U NPU - ;----------------------------------------------------- - isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 - { - ; Cache area (if used) - *.o (.bss.NoInit.ethos_u_cache) - - ; activation buffers a.k.a tensor arena when - ; memory mode sram only or shared sram - *.o (.bss.NoInit.activation_buf_sram) - } -} - -;--------------------------------------------------------- -; Second load region (DDR) -;--------------------------------------------------------- -LOAD_REGION_1 0x70000000 0x02000000 -{ - ;----------------------------------------------------- - ; 32 MiB of DDR space for neural network model, - ; input vectors and labels. If the activation buffer - ; size required by the network is bigger than the - ; SRAM size available, it is accommodated here. - ;----------------------------------------------------- - ddr.bin 0x70000000 ALIGN 16 0x02000000 - { - ; nn model's baked in input matrices - *.o (ifm) - - ; nn model's default space - *.o (nn_model) - - ; labels - *.o (labels) - - ; activation buffers a.k.a tensor arena when memory mode dedicated sram - *.o (activation_buf_dram) - } - - ;----------------------------------------------------- - ; First 256kiB of BRAM (FPGA SRAM) used for RO data. - ; Note: Total BRAM size available is 1MiB. - ;----------------------------------------------------- - bram.bin 0x11000000 ALIGN 8 0x00040000 - { - ; RO data (incl. unwinding tables for debugging) - .ANY (+RO-DATA) - } - - ;----------------------------------------------------- - ; 768 KiB of remaining part of the 1MiB BRAM used as - ; heap space. - ;----------------------------------------------------- - ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 - {} - - ;----------------------------------------------------- - ; The following regions are for use by the FVP to - ; allow loading or dumping of dynamic data into or - ; from the memory. These regions are mentioned in - ; the CMake subsystem profile. Do not change the - ; addresses and sizes below in isolation. - ;----------------------------------------------------- - ; 32 MiB of model space for run-time load of model - ;----------------------------------------------------- - runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 - {} - - ;----------------------------------------------------- - ; 16 MiB of IFM space for run-time loading (FVP only) - ;----------------------------------------------------- - runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 - {} - - ;----------------------------------------------------- - ; 16 MiB of OFM space for run-time loading (FVP only) - ;----------------------------------------------------- - runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 - {} -} diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld deleted file mode 100644 index 82cb18e..0000000 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -__STACK_SIZE = 0x00060000; -__HEAP_SIZE = 0x000C0000; - -/* System memory brief */ -MEMORY -{ - ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 - BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 - SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 - DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions ITCM and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text.at_itcm : - { - KEEP(*(.vectors)) - - /** - * All code goes here, with one exception of - * all_ops_resolver object file. This code - * instead placed on BRAM. See comment in the - * BRAM section for details. - **/ - *(EXCLUDE_FILE(*all_ops_resolver.o *hal.c.obj) .text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - KEEP(*(.eh_frame*)) - } > ITCM - - __exidx_start = .; - .ARM.exidx.at_itcm : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ITCM - __exidx_end = .; - - .zero.table.at_itcm : - { - . = ALIGN(4); - __zero_table_start__ = .; - - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ - - __zero_table_end__ = .; - } > ITCM - - .copy.table.at_itcm : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Section to be copied - part 1: any data to be placed in BRAM */ - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */ - - /* Section to be copied - part 2: RO data for for DTCM */ - LONG (__etext2) - LONG (__ro_data_start__) - LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */ - - __copy_table_end__ = .; - } > ITCM - - __itcm_total = ALIGN(4); - - ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow") - - .sram : - { - . = ALIGN(16); - /* Cache area (if used) */ - *(.bss.NoInit.ethos_u_cache) - . = ALIGN (16); - /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ - *(.bss.NoInit.activation_buf_sram) - . = ALIGN(16); - } > SRAM AT > SRAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > DTCM AT > DTCM - - .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > DTCM - PROVIDE(__stack = __StackTop); - ASSERT( - (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM), - "DTCM overflow") - - .ddr.at_ddr : - { - /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. - * Force the alignment here as a workaround */ - . = ALIGN(16); - /* nn model's baked in input matrices */ - *(ifm) - . = ALIGN(16); - /* nn model's default space */ - *(nn_model) - . = ALIGN (16); - /* labels */ - *(labels) - . = ALIGN (16); - /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ - *(activation_buf_dram) - . = ALIGN (16); - } > DDR AT > DDR - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in DTCM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .bram.at_ddr : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - KEEP(*(.jcr*)) - . = ALIGN(4); - - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - - /** - * Place the all ops resolver code data here. This accounts - * for ~4k worth of saving on the ITCM load region. It is - * only designed to be included (by default) for the inference - * runner use case. - **/ - *all_ops_resolver.o (*.text*) - . = ALIGN(4); - *hal.c.obj (*.text*) - . = ALIGN(4); - - __data_end__ = .; - } > BRAM - - __etext2 = __etext + (__data_end__ - __data_start__); - - .data.at_ddr : AT (__etext2) - { - . = ALIGN(4); - __ro_data_start__ = .; - - *(.rodata*) - . = ALIGN(4); - * (npu_driver_version) - . = ALIGN(4); - * (npu_driver_arch_version) - . = ALIGN(4); - - __ro_data_end__ = .; - } > BRAM - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > BRAM - - ASSERT ( - (__ro_data_end__ - __ro_data_start__) - + (__data_end__ - __data_start__) - + __HEAP_SIZE <= LENGTH(BRAM), - "BRAM overflow") -} diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct deleted file mode 100644 index 5825d47..0000000 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct +++ /dev/null @@ -1,122 +0,0 @@ -; Copyright (c) 2021 Arm Limited. All rights reserved. -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -; ************************************************************* -; *** Scatter-Loading Description File *** -; ************************************************************* -; Please see docs/sections/appendix.md for memory mapping information. -; -; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR -; sections => activation buffers and the model should only -; be placed in those regions. -; -;--------------------------------------------------------- -; First load region (ITCM) -;--------------------------------------------------------- -LOAD_REGION_0 0x00000000 0x00080000 -{ - ;----------------------------------------------------- - ; First part of code mem - 512kiB - ;----------------------------------------------------- - itcm.bin 0x00000000 0x00080000 - { - *.o (RESET, +First) - * (InRoot$$Sections) - - ; Essentially only RO-CODE, RO-DATA is in a - ; different region. - .ANY (+RO) - } - - ;----------------------------------------------------- - ; 128kiB of 512kiB DTCM is used for any other RW or ZI - ; data. Note: this region is internal to the Cortex-M - ; CPU. - ;----------------------------------------------------- - dtcm.bin 0x20000000 0x00020000 - { - ; Any R/W and/or zero initialised data - .ANY(+RW +ZI) - } - - ;----------------------------------------------------- - ; 384kiB of stack space within the DTCM region. See - ; `dtcm.bin` for the first section. Note: by virtue of - ; being part of DTCM, this region is only accessible - ; from Cortex-M55. - ;----------------------------------------------------- - ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 - {} - - ;----------------------------------------------------- - ; SSE-300's internal SRAM of 2MiB - reserved for - ; activation buffers. - ; This region should have 3 cycle read latency from - ; both Cortex-M55 and Ethos-U NPU - ;----------------------------------------------------- - isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 - { - ; Cache area (if used) - *.o (.bss.NoInit.ethos_u_cache) - - ; activation buffers a.k.a tensor arena when - ; memory mode sram only or shared sram - *.o (.bss.NoInit.activation_buf_sram) - } -} - -;--------------------------------------------------------- -; Second load region (DDR) -;--------------------------------------------------------- -LOAD_REGION_1 0x70000000 0x02000000 -{ - ;----------------------------------------------------- - ; 32 MiB of DDR space for neural network model, - ; input vectors and labels. If the activation buffer - ; size required by the network is bigger than the - ; SRAM size available, it is accommodated here. - ;----------------------------------------------------- - ddr.bin 0x70000000 ALIGN 16 0x02000000 - { - ; nn model's baked in input matrices - *.o (ifm) - - ; nn model's default space - *.o (nn_model) - - ; labels - *.o (labels) - - ; activation buffers a.k.a tensor arena when memory mode dedicated sram - *.o (activation_buf_dram) - } - - ;----------------------------------------------------- - ; First 256kiB of BRAM (FPGA SRAM) used for RO data. - ; Note: Total BRAM size available is 1MiB. - ;----------------------------------------------------- - bram.bin 0x11000000 ALIGN 8 0x00040000 - { - ; RO data (incl. unwinding tables for debugging) - .ANY (+RO-DATA) - } - - ;----------------------------------------------------- - ; 768 KiB of remaining part of the 1MiB BRAM used as - ; heap space. - ;----------------------------------------------------- - ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 - {} -} diff --git a/source/application/hal/platforms/native/utils/include/dummy_log.h b/source/application/hal/platforms/native/utils/include/dummy_log.h deleted file mode 100644 index 3df5c5c..0000000 --- a/source/application/hal/platforms/native/utils/include/dummy_log.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef DUMMY_LOG_H -#define DUMMY_LOG_H - -#include <stdio.h> - -#define LOG_LEVEL_TRACE 0 -#define LOG_LEVEL_DEBUG 1 -#define LOG_LEVEL_INFO 2 -#define LOG_LEVEL_WARN 3 -#define LOG_LEVEL_ERROR 4 - -#ifndef LOG_LEVEL -#define LOG_LEVEL LOG_LEVEL_INFO -#endif /*LOG_LEVEL*/ - -#define UNUSED(x) ((void)(x)) - -#if (LOG_LEVEL == LOG_LEVEL_TRACE) - #define trace(...) printf("TRACE - "); printf(__VA_ARGS__) -#else - #define trace(...) -#endif /* LOG_LEVEL == LOG_LEVEL_TRACE */ - -#if (LOG_LEVEL <= LOG_LEVEL_DEBUG) - #define debug(...) printf("DEBUG - "); printf(__VA_ARGS__) -#else - #define debug(...) -#endif /* LOG_LEVEL > LOG_LEVEL_TRACE */ - -#if (LOG_LEVEL <= LOG_LEVEL_INFO) - #define info(...) printf("INFO - "); printf(__VA_ARGS__) -#else - #define info(...) -#endif /* LOG_LEVEL > LOG_LEVEL_DEBUG */ - -#if (LOG_LEVEL <= LOG_LEVEL_WARN) - #define warn(...) printf("WARN - "); printf(__VA_ARGS__) -#else - #define warn(...) -#endif /* LOG_LEVEL > LOG_LEVEL_INFO */ - -#if (LOG_LEVEL <= LOG_LEVEL_ERROR) - #define printf_err(...) printf("ERROR - "); printf(__VA_ARGS__) -#else - #define printf_err(...) -#endif /* LOG_LEVEL > LOG_LEVEL_INFO */ - -#endif /* DUMMY_LOG_H */
\ No newline at end of file diff --git a/source/application/main/Classifier.cc b/source/application/main/Classifier.cc index a6ff532..6fabebe 100644 --- a/source/application/main/Classifier.cc +++ b/source/application/main/Classifier.cc @@ -16,15 +16,16 @@ */ #include "Classifier.hpp" -#include "hal.h" #include "TensorFlowLiteMicro.hpp" +#include "PlatformMath.hpp" +#include "log_macros.h" #include <vector> #include <string> #include <set> #include <cstdint> -#include <inttypes.h> -#include "PlatformMath.hpp" +#include <cinttypes> + namespace arm { namespace app { diff --git a/source/application/main/Main.cc b/source/application/main/Main.cc index 9622566..3a1c110 100644 --- a/source/application/main/Main.cc +++ b/source/application/main/Main.cc @@ -20,6 +20,7 @@ \****************************************************************************/ #include "hal.h" /* our hardware abstraction api */ +#include "log_macros.h" #include "TensorFlowLiteMicro.hpp" /* our inference logic api */ #include <cstdio> diff --git a/source/application/main/Mfcc.cc b/source/application/main/Mfcc.cc index 2d697ee..3bf5eb3 100644 --- a/source/application/main/Mfcc.cc +++ b/source/application/main/Mfcc.cc @@ -15,11 +15,11 @@ * limitations under the License. */ #include "Mfcc.hpp" - #include "PlatformMath.hpp" +#include "log_macros.h" #include <cfloat> -#include <inttypes.h> +#include <cinttypes> namespace arm { namespace app { diff --git a/source/application/main/UseCaseCommonUtils.cc b/source/application/main/UseCaseCommonUtils.cc index 67e784b..dd9a32d 100644 --- a/source/application/main/UseCaseCommonUtils.cc +++ b/source/application/main/UseCaseCommonUtils.cc @@ -16,7 +16,9 @@ */ #include "UseCaseCommonUtils.hpp" #include "InputFiles.hpp" -#include <inttypes.h> +#include "log_macros.h" + +#include <cinttypes> void DisplayCommonMenu() @@ -74,7 +76,7 @@ bool image::PresentInferenceResult( platform.data_psn->present_data_text( resultStr.c_str(), resultStr.size(), - dataPsnTxtStartX1, rowIdx1, 0); + dataPsnTxtStartX1, rowIdx1, false); rowIdx1 += dataPsnTxtYIncr; resultStr = std::to_string(i + 1) + ") " + results[i].m_label; @@ -105,7 +107,7 @@ void image::RgbToGrayscale(const uint8_t *srcPtr, uint8_t *dstPtr, const size_t } } -void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, std::string useCase) +void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, const std::string& useCase) { #if NUMBER_OF_FILES > 0 auto curImIdx = ctx.Get<uint32_t>(useCase); @@ -122,7 +124,7 @@ void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, std::string useCas #endif /* NUMBER_OF_FILES > 0 */ } -bool SetAppCtxIfmIdx(arm::app::ApplicationContext& ctx, uint32_t idx, std::string ctxIfmName) +bool SetAppCtxIfmIdx(arm::app::ApplicationContext& ctx, uint32_t idx, const std::string& ctxIfmName) { #if NUMBER_OF_FILES > 0 if (idx >= NUMBER_OF_FILES) { @@ -192,7 +194,7 @@ void DumpTensor(const TfLiteTensor* tensor, const size_t lineBreakForNumElements } const uint32_t tensorSz = tensor->bytes; - const uint8_t* tensorData = tflite::GetTensorData<uint8_t>(tensor); + const auto* tensorData = tflite::GetTensorData<uint8_t>(tensor); DumpTensorData(tensorData, tensorSz, lineBreakForNumElements); } diff --git a/source/application/main/include/Classifier.hpp b/source/application/main/include/Classifier.hpp index d899e8e..d641c22 100644 --- a/source/application/main/include/Classifier.hpp +++ b/source/application/main/include/Classifier.hpp @@ -50,7 +50,7 @@ namespace app { TfLiteTensor* outputTensor, std::vector<ClassificationResult>& vecResults, const std::vector <std::string>& labels, uint32_t topNCount, - bool use_softmax = false); + bool use_softmax); /** * @brief Populate the elements of the Classification Result object. diff --git a/source/application/main/include/DataStructures.hpp b/source/application/main/include/DataStructures.hpp index d369cb6..0616839 100644 --- a/source/application/main/include/DataStructures.hpp +++ b/source/application/main/include/DataStructures.hpp @@ -17,8 +17,6 @@ #ifndef DATA_STRUCTURES_HPP #define DATA_STRUCTURES_HPP -#include "hal.h" - #include <iterator> namespace arm { @@ -50,7 +48,7 @@ namespace app { Array2d(unsigned rows, unsigned cols): m_rows(rows), m_cols(cols) { if (rows == 0 || cols == 0) { - printf_err("Array2d constructor has 0 size.\n"); + printf("Array2d constructor has 0 size.\n"); m_data = nullptr; return; } diff --git a/source/application/main/include/UseCaseCommonUtils.hpp b/source/application/main/include/UseCaseCommonUtils.hpp index 84b5de3..cd0cb69 100644 --- a/source/application/main/include/UseCaseCommonUtils.hpp +++ b/source/application/main/include/UseCaseCommonUtils.hpp @@ -24,7 +24,7 @@ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "Classifier.hpp" /* Classifier. */ #include "InputFiles.hpp" -#include <inttypes.h> +#include <cinttypes> /* Helper macro to convert RGB888 to RGB565 format. */ @@ -33,8 +33,8 @@ ((B8>>3) & 0x1F)) constexpr uint16_t COLOR_BLACK = 0; -constexpr uint16_t COLOR_GREEN = RGB888_TO_RGB565( 0, 255, 0); // 2016; -constexpr uint16_t COLOR_YELLOW = RGB888_TO_RGB565(255, 255, 0); // 65504; +constexpr uint16_t COLOR_GREEN = RGB888_TO_RGB565( 0u, 255u, 0u); // 2016; +constexpr uint16_t COLOR_YELLOW = RGB888_TO_RGB565(255u, 255u, 0u); // 65504; void DisplayCommonMenu(); @@ -72,7 +72,7 @@ namespace image{ * @param[in,out] ctx Pointer to the application context object. * @param[in] useCase Use case name **/ -void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, std::string useCase); +void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, const std::string& useCase); /** * @brief Helper function to set the input feature map index. @@ -81,7 +81,7 @@ void IncrementAppCtxIfmIdx(arm::app::ApplicationContext& ctx, std::string useCas * @param[in] ctxIfmName Input Feature Map name * @return true if index is set, false otherwise. **/ -bool SetAppCtxIfmIdx(arm::app::ApplicationContext& ctx, uint32_t idx, std::string ctxIfmName); +bool SetAppCtxIfmIdx(arm::app::ApplicationContext& ctx, uint32_t idx, const std::string& ctxIfmName); namespace common { diff --git a/source/application/profiler/Profiler.cc b/source/application/profiler/Profiler.cc index c2b8f2a..efbc64d 100644 --- a/source/application/profiler/Profiler.cc +++ b/source/application/profiler/Profiler.cc @@ -15,9 +15,9 @@ * limitations under the License. */ #include "Profiler.hpp" +#include "log_macros.h" #include <cstring> -#include <iomanip> namespace arm { namespace app { diff --git a/source/application/tensorflow-lite-micro/Model.cc b/source/application/tensorflow-lite-micro/Model.cc index acc2f0e..adcf8d7 100644 --- a/source/application/tensorflow-lite-micro/Model.cc +++ b/source/application/tensorflow-lite-micro/Model.cc @@ -15,19 +15,14 @@ * limitations under the License. */ #include "Model.hpp" +#include "log_macros.h" -#include "hal.h" - -#include <cstdint> -#include <inttypes.h> +#include <cinttypes> /* Initialise the model */ arm::app::Model::~Model() { - if (this->m_pInterpreter) { - delete this->m_pInterpreter; - } - + delete this->m_pInterpreter; /** * No clean-up function available for allocator in TensorFlow Lite Micro yet. **/ @@ -222,7 +217,7 @@ void arm::app::Model::LogInterpreterInfo() tflite::GetRegistrationFromOpCode(opcode, this->GetOpResolver(), this->m_pErrorReporter, ®); - std::string opName{""}; + std::string opName; if (reg) { if (tflite::BuiltinOperator_CUSTOM == reg->builtin_code) { @@ -262,7 +257,7 @@ bool arm::app::Model::ContainsEthosUOperator() const auto builtin_code = tflite::GetBuiltinCode(opcode); if ((builtin_code == tflite::BuiltinOperator_CUSTOM) && ( nullptr != opcode->custom_code()) && - ( 0 == std::string(opcode->custom_code()->c_str()).compare("ethos-u"))) + ( "ethos-u" == std::string(opcode->custom_code()->c_str()))) { return true; } @@ -350,11 +345,7 @@ bool arm::app::Model::ShowModelInfoHandler() info("Model info:\n"); this->LogInterpreterInfo(); -#if defined(ARM_NPU) - info("Use of Arm uNPU is enabled\n"); -#else /* ARM_NPU */ - info("Use of Arm uNPU is disabled\n"); -#endif /* ARM_NPU */ + info("The model is optimised for Ethos-U NPU: %s.\n", this->ContainsEthosUOperator()? "yes": "no"); return true; } diff --git a/source/application/tensorflow-lite-micro/TensorFlowLiteMicro.cc b/source/application/tensorflow-lite-micro/TensorFlowLiteMicro.cc index 0b08513..e82e9b5 100644 --- a/source/application/tensorflow-lite-micro/TensorFlowLiteMicro.cc +++ b/source/application/tensorflow-lite-micro/TensorFlowLiteMicro.cc @@ -16,8 +16,6 @@ */ #include "TensorFlowLiteMicro.hpp" -#include "hal.h" - void PrintTensorFlowVersion() {} diff --git a/source/hal/CMakeLists.txt b/source/hal/CMakeLists.txt new file mode 100644 index 0000000..ea19de5 --- /dev/null +++ b/source/hal/CMakeLists.txt @@ -0,0 +1,202 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# HAL library # +######################################################### + +cmake_minimum_required(VERSION 3.15.6) + +set(HAL_TARGET hal) + +project(${HAL_TARGET} + DESCRIPTION "HAL library" + LANGUAGES C CXX) + +# Create static library +add_library(${HAL_TARGET} STATIC) + +# Select which profile needs to be used: +if (${CMAKE_CROSSCOMPILING}) + set(PLATFORM_PROFILE bare-metal) +else() + set(PLATFORM_PROFILE native) +endif() + +set(PLATFORM_PROFILE_DIR profiles/${PLATFORM_PROFILE}) + +## Common include directories - public +target_include_directories(${HAL_TARGET} + PUBLIC + include + ${PLATFORM_PROFILE_DIR}/timer/include + ${PLATFORM_PROFILE_DIR}/utils/include) + +## Common sources for all profiles +target_sources(${HAL_TARGET} + PRIVATE + hal.c + ${PLATFORM_PROFILE_DIR}/data_presentation/data_psn.c + ${PLATFORM_PROFILE_DIR}/data_acquisition/data_acq.c + ${PLATFORM_PROFILE_DIR}/timer/platform_timer.c + ${PLATFORM_PROFILE_DIR}/utils/system_init.c) + +if (DEFINED VERIFY_TEST_OUTPUT) + message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}") + target_compile_definitions(${HAL_TARGET} PUBLIC + VERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}) +endif () + +############################ bare-metal profile ############################# +if (PLATFORM_PROFILE STREQUAL bare-metal) + + if (NOT DEFINED PLATFORM_DRIVERS_DIR) + message(FATAL_ERROR "PLATFORM_DRIVERS_DIR need to be defined for this target") + endif() + + ## Additional include directories - public + target_include_directories(${HAL_TARGET} + PUBLIC + ${PLATFORM_PROFILE_DIR}/bsp/include) + + ## Additional include directories - private + target_include_directories(${HAL_TARGET} + PRIVATE + ${PLATFORM_PROFILE_DIR}/data_presentation/lcd/include) + + ## Additional sources - public + target_sources(${HAL_TARGET} + PUBLIC + ${PLATFORM_PROFILE_DIR}/bsp/retarget.c) + + ## Additional sources - private + target_sources(${HAL_TARGET} + PRIVATE + ${PLATFORM_PROFILE_DIR}/data_presentation/lcd/lcd_img.c) + + ## Compile definition: + target_compile_definitions(${HAL_TARGET} + PUBLIC + PLATFORM_HAL=PLATFORM_CORTEX_M_BAREMETAL) + + # Add dependencies for platform_driver first, in case they are needed by it. + add_subdirectory(cmsis_device ${CMAKE_BINARY_DIR}/cmsis_device) + + # Add platform-drivers target + add_subdirectory(${PLATFORM_DRIVERS_DIR} ${CMAKE_BINARY_DIR}/platform_driver) + + # Link time library targets: + target_link_libraries(${HAL_TARGET} + PUBLIC + log + platform-drivers) + + # If Ethos-U is enabled, we need the driver library too + if (ETHOS_U_NPU_ENABLED) + + if (NOT DEFINED ETHOS_U_NPU_DRIVER_SRC_PATH) + message(FATAL_ERROR "ETHOS_U_NPU_DRIVER_SRC_PATH should" + " be defined when ETHOS_U_NPU_ENABLED=${ETHOS_U_NPU_ENABLED}") + endif() + + # Timing adapter, should, in theory be part of platform-drivers. For now + # limiting the scope of refactoring - but in future, TA should not be + # needed if not available on the target platform. + if (NOT DEFINED ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH) + message(FATAL_ERROR "ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH should" + " be defined when ETHOS_U_NPU_ENABLED=${ETHOS_U_NPU_ENABLED}") + endif() + + target_compile_definitions(${HAL_TARGET} + PUBLIC + ARM_NPU) + + # For the driver, we need to provide the CMSIS_PATH variable + set(CMSIS_PATH ${CMSIS_SRC_PATH} CACHE PATH "Path to CMSIS directory") + add_subdirectory(${ETHOS_U_NPU_DRIVER_SRC_PATH} ${CMAKE_BINARY_DIR}/ethos-u-driver) + add_subdirectory(${ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH} ${CMAKE_BINARY_DIR}/timing-adapter) + + target_link_libraries(${HAL_TARGET} + PUBLIC + ethosu_core_driver + timing_adapter) + + if (NOT DEFINED ETHOS_U_NPU_ID) + set(ETHOS_U_NPU_ID U55) + endif() + + if (NOT DEFINED ETHOS_U_NPU_MEMORY_MODE) + set(ETHOS_U_NPU_MEMORY_MODE Shared_Sram) + endif() + + if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only) + if (ETHOS_U_NPU_ID STREQUAL U55) + set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEM_MODE_SRAM_ONLY") + else () + message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `sram_only` can be used only for Ethos-U55.") + endif () + + elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram) + # Shared Sram can be used for Ethos-U55 and Ethos-U65 + set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM") + + elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram) + # Dedicated Sram is used only for Ethos-U65 + if (ETHOS_U_NPU_ID STREQUAL U65) + set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM") + else () + message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.") + endif () + else () + message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}") + endif () + + target_compile_definitions(${HAL_TARGET} + PUBLIC + ${ETHOS_U_NPU_MEMORY_MODE_FLAG}) + endif() + +############################ native profile ############################# +elseif (PLATFORM_PROFILE STREQUAL native) + ## Additional include directories - private + target_include_directories(${HAL_TARGET} + PRIVATE + ${PLATFORM_PROFILE_DIR}/data_presentation/log/include) + + ## Additional sources - private + target_sources(${HAL_TARGET} + PRIVATE + ${PLATFORM_PROFILE_DIR}/data_presentation/log/log.c) + + ## Compile definition: + target_compile_definitions(${HAL_TARGET} + PUBLIC + PLATFORM_HAL=PLATFORM_UNKNOWN_LINUX_OS + ACTIVATION_BUF_SRAM_SZ=0) + + target_link_libraries(${HAL_TARGET} + PUBLIC + log) + +endif() + +# Display status: +message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) +message(STATUS "*******************************************************") +message(STATUS "Library : " ${HAL_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/hal/cmsis_device/CMakeLists.txt b/source/hal/cmsis_device/CMakeLists.txt new file mode 100644 index 0000000..9f834d5 --- /dev/null +++ b/source/hal/cmsis_device/CMakeLists.txt @@ -0,0 +1,67 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# Generic CMSIS Start up library for Cortex-M targets # +######################################################### +cmake_minimum_required(VERSION 3.15.6) + +set(CMSIS_DEVICE_TARGET cmsis_device) + +project(${CMSIS_DEVICE_TARGET} + DESCRIPTION "Generic CMSIS start up file for Cortex-M targets" + LANGUAGES C CXX ASM) + +# 1. We should be cross-compiling (non-native target) +if (NOT ${CMAKE_CROSSCOMPILING}) + message(FATAL_ERROR "No ${CMSIS_DEVICE_TARGET} support for this target.") +endif() + +# 2. Check if CMSIS sources have been defined +if (NOT DEFINED CMSIS_SRC_PATH) + message(FATAL_ERROR "CMSIS_SRC_PATH path should be defined for ${CMSIS_DEVICE_TARGET}.") +endif() + +# 3. Create static library +add_library(${CMSIS_DEVICE_TARGET} STATIC) + +## Include directories - public +target_include_directories(${CMSIS_DEVICE_TARGET} + PUBLIC + include + ${CMSIS_SRC_PATH}/CMSIS/Core/Include + ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include + ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include/Template) + +## Sources +target_sources(${CMSIS_DEVICE_TARGET} + PRIVATE + source/cmsis.c + source/irqs.c) + +# Tell linker that reset interrupt handler is our entry point +target_link_options( + ${CMSIS_DEVICE_TARGET} + INTERFACE + --entry Reset_Handler) + +# 4 Display status: +message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) +message(STATUS "*******************************************************") +message(STATUS "Library : " ${CMSIS_DEVICE_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h b/source/hal/cmsis_device/include/cmsis.h index 9d6326a..9d6326a 100644 --- a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h +++ b/source/hal/cmsis_device/include/cmsis.h diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h b/source/hal/cmsis_device/include/irqs.h index 0d8dec6..5ddda97 100644 --- a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h +++ b/source/hal/cmsis_device/include/irqs.h @@ -21,8 +21,6 @@ extern "C" { #endif -#include "peripheral_irqs.h" - #include <stdint.h> /* Interrupt handler function type. */ diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c b/source/hal/cmsis_device/source/cmsis.c index 9cf6213..9cf6213 100644 --- a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c +++ b/source/hal/cmsis_device/source/cmsis.c diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/irqs.c b/source/hal/cmsis_device/source/irqs.c index 7d8aa06..7d8aa06 100644 --- a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/irqs.c +++ b/source/hal/cmsis_device/source/irqs.c diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/glcd_mps3.c b/source/hal/components/lcd_mps3/glcd_mps3.c index 530be4f..08d4c5e 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/glcd_mps3.c +++ b/source/hal/components/lcd_mps3/glcd_mps3.c @@ -16,7 +16,7 @@ */ #include "glcd_mps3.h" -#include "bsp_core_log.h" +#include "log_macros.h" #include "font_9x15_h.h" #include "smm_mps3.h" diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/font_9x15_h.h b/source/hal/components/lcd_mps3/include/font_9x15_h.h index b8b6bdc..b8b6bdc 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/font_9x15_h.h +++ b/source/hal/components/lcd_mps3/include/font_9x15_h.h diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/glcd_mps3.h b/source/hal/components/lcd_mps3/include/glcd_mps3.h index c2810c0..c2810c0 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/glcd_mps3.h +++ b/source/hal/components/lcd_mps3/include/glcd_mps3.h diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-core/include/uart_stdout.h b/source/hal/components/uart_cmsdk/include/uart_stdout.h index 9c5fbcf..9c5fbcf 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-core/include/uart_stdout.h +++ b/source/hal/components/uart_cmsdk/include/uart_stdout.h diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c b/source/hal/components/uart_cmsdk/uart_cmsdk.c index 35d4160..35d4160 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c +++ b/source/hal/components/uart_cmsdk/uart_cmsdk.c diff --git a/source/hal/components/uart_pl011/include/uart_stdout.h b/source/hal/components/uart_pl011/include/uart_stdout.h new file mode 100644 index 0000000..9c5fbcf --- /dev/null +++ b/source/hal/components/uart_pl011/include/uart_stdout.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef UART_STDOUT_H +#define UART_STDOUT_H + +#include <stdbool.h> + +/** + * @brief Initialised the UART block. + **/ +extern void UartStdOutInit(void); + +/** + * @brief Transmits a character over UART (blocking call). + * @param[in] my_ch Character to be transmitted. + * @return Character transmitted. + **/ +extern unsigned char UartPutc(unsigned char my_ch); + +/** + * @brief Receives a character from the UART block (blocking call). + * @return Character received. + **/ +extern unsigned char UartGetc(void); + +/** + * @brief Reads characters from the UART block until a line feed or + * carriage return terminates the function. NULL character + * also terminates the function, error is returned. + * @param[out] lp Characters read from the UART block. + * @param[in] len Character to be transmitted. + * @return true if successful, false otherwise. + **/ +extern bool GetLine(char *lp, unsigned int len); + +/** + * @brief Terminates UART simulation. This is useful when a Fixed + * Virtual Platform's session needs to be gracefully terminated. + * @param[in] code Terminating code displayed on the UART before the end of the simulation. + **/ +extern void UartEndSimulation(int code); + +#endif /* UART_STDOUT_H */ diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c b/source/hal/components/uart_pl011/uart_pl011.c index 1cbf70c..1cbf70c 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/uart_pl011.c +++ b/source/hal/components/uart_pl011/uart_pl011.c diff --git a/source/application/hal/hal.c b/source/hal/hal.c index c067ba2..ff470d5 100644 --- a/source/application/hal/hal.c +++ b/source/hal/hal.c @@ -18,6 +18,7 @@ #include "hal_config.h" /* HAL configuration */ #include "system_init.h" +#include "log_macros.h" #include <stdio.h> #include <assert.h> @@ -27,7 +28,10 @@ #include "ethosu_mem_config.h" /* Arm Ethos-U memory config */ #include "ethosu_driver.h" /* Arm Ethos-U driver header */ #include "timing_adapter.h" /* Arm Ethos-U timing adapter driver header */ + +#if defined(TIMING_ADAPTER_AVAILABLE) #include "timing_adapter_settings.h" /* Arm Ethos-U timing adapter settings */ +#endif /* defined(TIMING_ADAPTER_AVAILABLE) */ struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */ @@ -177,64 +181,66 @@ static void arm_npu_irq_init(void) ethosu_irqnum, arm_npu_irq_handler); } -static int _arm_npu_timing_adapter_init(void) -{ -#if defined (TA0_BASE) - struct timing_adapter ta_0; - struct timing_adapter_settings ta_0_settings = { - .maxr = TA0_MAXR, - .maxw = TA0_MAXW, - .maxrw = TA0_MAXRW, - .rlatency = TA0_RLATENCY, - .wlatency = TA0_WLATENCY, - .pulse_on = TA0_PULSE_ON, - .pulse_off = TA0_PULSE_OFF, - .bwcap = TA0_BWCAP, - .perfctrl = TA0_PERFCTRL, - .perfcnt = TA0_PERFCNT, - .mode = TA0_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA0_HISTBIN, - .histcnt = TA0_HISTCNT - }; - - if (0 != ta_init(&ta_0, TA0_BASE)) { - printf_err("TA0 initialisation failed\n"); - return 1; - } +#if defined(TIMING_ADAPTER_AVAILABLE) + static int _arm_npu_timing_adapter_init(void) + { + #if defined (TA0_BASE) + struct timing_adapter ta_0; + struct timing_adapter_settings ta_0_settings = { + .maxr = TA0_MAXR, + .maxw = TA0_MAXW, + .maxrw = TA0_MAXRW, + .rlatency = TA0_RLATENCY, + .wlatency = TA0_WLATENCY, + .pulse_on = TA0_PULSE_ON, + .pulse_off = TA0_PULSE_OFF, + .bwcap = TA0_BWCAP, + .perfctrl = TA0_PERFCTRL, + .perfcnt = TA0_PERFCNT, + .mode = TA0_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = TA0_HISTBIN, + .histcnt = TA0_HISTCNT + }; + + if (0 != ta_init(&ta_0, TA0_BASE)) { + printf_err("TA0 initialisation failed\n"); + return 1; + } - ta_set_all(&ta_0, &ta_0_settings); -#endif /* defined (TA0_BASE) */ - -#if defined (TA1_BASE) - struct timing_adapter ta_1; - struct timing_adapter_settings ta_1_settings = { - .maxr = TA1_MAXR, - .maxw = TA1_MAXW, - .maxrw = TA1_MAXRW, - .rlatency = TA1_RLATENCY, - .wlatency = TA1_WLATENCY, - .pulse_on = TA1_PULSE_ON, - .pulse_off = TA1_PULSE_OFF, - .bwcap = TA1_BWCAP, - .perfctrl = TA1_PERFCTRL, - .perfcnt = TA1_PERFCNT, - .mode = TA1_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA1_HISTBIN, - .histcnt = TA1_HISTCNT - }; - - if (0 != ta_init(&ta_1, TA1_BASE)) { - printf_err("TA1 initialisation failed\n"); - return 1; - } + ta_set_all(&ta_0, &ta_0_settings); + #endif /* defined (TA0_BASE) */ + + #if defined (TA1_BASE) + struct timing_adapter ta_1; + struct timing_adapter_settings ta_1_settings = { + .maxr = TA1_MAXR, + .maxw = TA1_MAXW, + .maxrw = TA1_MAXRW, + .rlatency = TA1_RLATENCY, + .wlatency = TA1_WLATENCY, + .pulse_on = TA1_PULSE_ON, + .pulse_off = TA1_PULSE_OFF, + .bwcap = TA1_BWCAP, + .perfctrl = TA1_PERFCTRL, + .perfcnt = TA1_PERFCNT, + .mode = TA1_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = TA1_HISTBIN, + .histcnt = TA1_HISTCNT + }; + + if (0 != ta_init(&ta_1, TA1_BASE)) { + printf_err("TA1 initialisation failed\n"); + return 1; + } - ta_set_all(&ta_1, &ta_1_settings); -#endif /* defined (TA1_BASE) */ + ta_set_all(&ta_1, &ta_1_settings); + #endif /* defined (TA1_BASE) */ - return 0; -} + return 0; + } +#endif /* defined(TIMING_ADAPTER_AVAILABLE) */ static int arm_npu_init(void) { @@ -242,9 +248,11 @@ static int arm_npu_init(void) /* If the platform has timing adapter blocks along with Ethos-U core * block, initialise them here. */ +#if defined(TIMING_ADAPTER_AVAILABLE) if (0 != (err = _arm_npu_timing_adapter_init())) { return err; } +#endif /* defined(TIMING_ADAPTER_AVAILABLE) */ /* Initialise the IRQ */ arm_npu_irq_init(); @@ -268,16 +276,16 @@ static int arm_npu_init(void) /* Get Ethos-U version */ struct ethosu_driver_version driver_version; struct ethosu_hw_info hw_info; - + ethosu_get_driver_version(&driver_version); ethosu_get_hw_info(ðosu_drv, &hw_info); info("Ethos-U version info:\n"); - info("\tArch: v%"PRIu32".%"PRIu32".%"PRIu32"\n", + info("\tArch: v%"PRIu32".%"PRIu32".%"PRIu32"\n", hw_info.version.arch_major_rev, hw_info.version.arch_minor_rev, hw_info.version.arch_patch_rev); - info("\tDriver: v%"PRIu8".%"PRIu8".%"PRIu8"\n", + info("\tDriver: v%"PRIu8".%"PRIu8".%"PRIu8"\n", driver_version.major, driver_version.minor, driver_version.patch); diff --git a/source/application/hal/include/data_acq.h b/source/hal/include/data_acq.h index 965fbe5..965fbe5 100644 --- a/source/application/hal/include/data_acq.h +++ b/source/hal/include/data_acq.h diff --git a/source/application/hal/include/data_psn.h b/source/hal/include/data_psn.h index 8c14c77..8c14c77 100644 --- a/source/application/hal/include/data_psn.h +++ b/source/hal/include/data_psn.h diff --git a/source/application/hal/include/hal.h b/source/hal/include/hal.h index a192ea7..a192ea7 100644 --- a/source/application/hal/include/hal.h +++ b/source/hal/include/hal.h diff --git a/source/application/hal/include/hal_config.h b/source/hal/include/hal_config.h index 55db973..ca32f4e 100644 --- a/source/application/hal/include/hal_config.h +++ b/source/hal/include/hal_config.h @@ -30,11 +30,7 @@ #if ((PLATFORM_HAL) == PLATFORM_CORTEX_M_BAREMETAL) #include "bsp.h" -#elif ((PLATFORM_HAL) == PLATFORM_UNKNOWN_LINUX_OS) - #include "dummy_log.h" -#else - #error "Invalid platform!" -#endif /* PLATFORM_HAL==PLATFORM_CORTEX_M_BAREMETAL */ +#endif #if !defined (DESIGN_NAME) #define DESIGN_NAME ("N/A") diff --git a/source/application/hal/include/timer.h b/source/hal/include/timer.h index 426a42f..56aad5b 100644 --- a/source/application/hal/include/timer.h +++ b/source/hal/include/timer.h @@ -18,14 +18,7 @@ #define HAL_TIMER_H #include "hal_config.h" - -#if ((PLATFORM_HAL) == PLATFORM_CORTEX_M_BAREMETAL) -#include "baremetal_timer.h" -#elif ((PLATFORM_HAL) == PLATFORM_UNKNOWN_LINUX_OS) -#include "native_timer.h" -#else -#error "Platform does not support a timer API" -#endif /* PLATFORM_HAL */ +#include "platform_timer.h" /** Struct for describing the capabilities available for * the timer provided by HAL */ diff --git a/source/hal/platform/mps3/CMakeLists.txt b/source/hal/platform/mps3/CMakeLists.txt new file mode 100644 index 0000000..ad510ee --- /dev/null +++ b/source/hal/platform/mps3/CMakeLists.txt @@ -0,0 +1,114 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# MPS3 platform support library # +######################################################### + +cmake_minimum_required(VERSION 3.15.6) +set(PLATFORM_DRIVERS_TARGET platform-drivers) +project(${PLATFORM_DRIVERS_TARGET} + DESCRIPTION "Platform drivers library for MPS3 FPGA/FVP targets" + LANGUAGES C CXX ASM) + +# 1. We should be cross-compiling (MPS3 taregt only runs Cortex-M targets) +if (NOT ${CMAKE_CROSSCOMPILING}) + message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.") +endif() + +# 2. Set the platform cmake descriptor file +if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE) + set(PLATFORM_CMAKE_DESCRIPTOR_FILE + cmake/subsystem-profiles/corstone-sse-300.cmake + CACHE PATH + "Platform's CMake descriptor file path") +endif() + +## Include the platform cmake descriptor file +include(${PLATFORM_CMAKE_DESCRIPTOR_FILE}) + +# 3. Generate sources: +if (NOT DEFINED SOURCE_GEN_DIR) + set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp) +endif() + +set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template) +set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template) +set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template) + +configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h") +configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h") +configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h") + +# If a TA config file is provided, we generate a settings file +if (DEFINED TA_CONFIG_FILE) + include(${TA_CONFIG_FILE}) + set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/timing_adapter_settings.template) + configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h") +endif() + +# 4. Create static library +add_library(${PLATFORM_DRIVERS_TARGET} STATIC) + +## Include directories - public +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + include + ${SOURCE_GEN_DIR}) + +## Platform sources +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/device_mps3.c + source/timer_mps3.c) + +## Platform component: uart +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_cmsdk/uart_cmsdk.c) +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_cmsdk/include) + +## Platform component: LCD +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/lcd_mps3/glcd_mps3.c) +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/lcd_mps3/include) + +## This target provides the following definitions for MPS3 specific behaviour +## TODO: We should aim to remove this now with platform refactoring.. +target_compile_definitions(${PLATFORM_DRIVERS_TARGET} + PUBLIC + MPS3_PLATFORM + ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ} + $<$<BOOL:TA_CONFIG_FILE>:TIMING_ADAPTER_AVAILABLE>) + +# 5. Add dependencies: + +target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC + cmsis_device + log) + +# 6 Display status: +message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) +message(STATUS "*******************************************************") +message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/hal/platform/mps3/cmake/subsystem-profiles/corstone-sse-300.cmake b/source/hal/platform/mps3/cmake/subsystem-profiles/corstone-sse-300.cmake new file mode 100644 index 0000000..eec6fde --- /dev/null +++ b/source/hal/platform/mps3/cmake/subsystem-profiles/corstone-sse-300.cmake @@ -0,0 +1,319 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2021 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design +################################################################################################### +# Mem sizes # +################################################################################################### +set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") +set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks") +set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB") +set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB") +set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB") +set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB") +set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") + +################################################################################################### +# Base addresses for memory regions # +################################################################################################### +set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") +set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") +set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") +set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address") +set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address") +set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address") +set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") +set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") +set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") +set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") +set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") + +set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") +set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") +set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") +set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address") +set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address") +set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address") +set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address") +set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address") +set(QSPI_SRAM_BASE_S "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address") +set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") +set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") +set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") +set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") + +################################################################################################### +# Application specific config # +################################################################################################### +set(APP_NOTE "AN552") +set(DESIGN_NAME "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name") + +# The following parameter is based on the linker/scatter script for SSE-300. +# Do not change this parameter in isolation. +# SRAM size reserved for activation buffers +math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) + +################################################################################################### +# Base addresses for dynamic loads (to be used for FVP form only) # +################################################################################################### +# This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these +# parameters in isolation. +set(DYNAMIC_MODEL_BASE "${DDR4_BLK1_BASE_S}" CACHE STRING + "Region to be used for dynamic load of model into memory") +set(DYNAMIC_MODEL_SIZE "0x02000000" CACHE STRING "Size of the space reserved for the model") +math(EXPR DYNAMIC_IFM_BASE "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL) +set(DYNAMIC_IFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the IFM") +math(EXPR DYNAMIC_OFM_BASE "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL) +set(DYNAMIC_OFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the OFM") + +################################################################################################### +# Base addresses for peripherals - non secure # +################################################################################################### +set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)") +set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)") +set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)") +set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)") +set(FMC_CMDSK_GPIO_BASE0 "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)") +set(FMC_CMDSK_GPIO_BASE1 "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)") +set(FMC_CMDSK_GPIO_BASE2 "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)") +set(FMC_USER_AHB_BASE "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)") +set(DMA0_BASE "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)") +set(DMA1_BASE "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)") +set(DMA2_BASE "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)") +set(DMA3_BASE "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)") + +set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)") +set(USB_BASE "0x41500000" CACHE STRING "USB Base Address (1MB)") + +set(USER_APB0_BASE "0x41700000" CACHE STRING "User APB0") +set(USER_APB1_BASE "0x41701000" CACHE STRING "User APB1") +set(USER_APB2_BASE "0x41702000" CACHE STRING "User APB2") +set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3") + +set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ") +set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ") + +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) + +set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ") +set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ") +set(MPS3_SSP2_BASE "0x49202000" CACHE STRING "ADC SPI PL022 Base Address") +set(MPS3_SSP3_BASE "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address") +set(MPS3_SSP4_BASE "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address") +set(MPS3_I2C2_BASE "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ") +set(MPS3_I2C3_BASE "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ") + +set(USER_APB_BASE "0x49207000" CACHE STRING "User APB") +set(MPS3_I2C5_BASE "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") + +set(MPS3_SCC_BASE "0x49300000" CACHE STRING "SCC Base Address ") +set(MPS3_AAIC_I2S_BASE "0x49301000" CACHE STRING "Audio Interface I2S Base Address ") +set(MPS3_FPGAIO_BASE "0x49302000" CACHE STRING "FPGA IO Base Address ") + +set(CMSDK_UART0_BASE "0x49303000" CACHE STRING "UART 0 Base Address ") +set(CMSDK_UART1_BASE "0x49304000" CACHE STRING "UART 1 Base Address ") +set(CMSDK_UART2_BASE "0x49305000" CACHE STRING "UART 2 Base Address ") +set(CMSDK_UART3_BASE "0x49306000" CACHE STRING "UART 3 Base Address Shield 0") +set(CMSDK_UART4_BASE "0x49307000" CACHE STRING "UART 4 Base Address Shield 1") +set(CMSDK_UART5_BASE "0x49308000" CACHE STRING "UART 5 Base Address ") + +set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ") +set(RTC_BASE "0x4930B000" CACHE STRING "RTC Base address ") + +################################################################################################### +# Base addresses for peripherals - secure # +################################################################################################### +set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)") +set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)") +set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)") +set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)") + +set(SEC_AHB_USER0_BASE "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)") +set(SEC_AHB_USER1_BASE "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)") +set(SEC_AHB_USER2_BASE "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)") +set(SEC_AHB_USER3_BASE "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)") + +set(SEC_DMA0_BASE "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)") +set(SEC_DMA1_BASE "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)") +set(SEC_DMA2_BASE "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)") +set(SEC_DMA3_BASE "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)") + +set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)") +set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address (1MB)") + +set(SEC_USER_APB0_BASE "0x51700000" CACHE STRING "User APB0 Base Address") +set(SEC_USER_APB1_BASE "0x51701000" CACHE STRING "User APB1 Base Address") +set(SEC_USER_APB2_BASE "0x51702000" CACHE STRING "User APB2 Base Address") +set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address") + +set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ") +set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ") + +if (ETHOS_U_NPU_ENABLED) + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) + +set(SEC_MPS3_I2C0_BASE "0x59200000" CACHE STRING "Touch Screen I2C Base Address ") +set(SEC_MPS3_I2C1_BASE "0x59201000" CACHE STRING "Audio Interface I2C Base Address ") +set(SEC_MPS3_SSP2_BASE "0x59202000" CACHE STRING "ADC SPI PL022 Base Address") +set(SEC_MPS3_SSP3_BASE "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address") +set(SEC_MPS3_SSP4_BASE "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address") +set(SEC_MPS3_I2C2_BASE "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ") +set(SEC_MPS3_I2C3_BASE "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ") +set(SEC_USER_APB_BASE "0x59207000" CACHE STRING "User APB Base Address") +set(SEC_MPS3_I2C5_BASE "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") + +set(SEC_MPS3_SCC_BASE "0x59300000" CACHE STRING "SCC Base Address ") +set(SEC_MPS3_AAIC_I2S_BASE "0x59301000" CACHE STRING "Audio Interface I2S Base Address ") +set(SEC_MPS3_FPGAIO_BASE "0x59302000" CACHE STRING "FPGA IO Base Address ") + +set(SEC_CMSDK_UART0_BASE "0x59303000" CACHE STRING "UART 0 Base Address ") +set(SEC_CMSDK_UART1_BASE "0x59304000" CACHE STRING "UART 1 Base Address ") +set(SEC_CMSDK_UART2_BASE "0x59305000" CACHE STRING "UART 2 Base Address ") +set(SEC_CMSDK_UART3_BASE "0x59306000" CACHE STRING "UART 3 Base Address Shield 0") +set(SEC_CMSDK_UART4_BASE "0x59307000" CACHE STRING "UART 4 Base Address Shield 1") +set(SEC_CMSDK_UART5_BASE "0x59308000" CACHE STRING "UART 5 Base Address ") + +set(SEC_CLCD_CONFIG_BASE "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ") +set(SEC_RTC_BASE "0x5930B000" CACHE STRING "RTC Base address ") + +################################################################################################### +# MPCs # +################################################################################################### +set(MPC_ISRAM0_BASE_S "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address") +set(MPC_ISRAM1_BASE_S "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address") +set(MPC_BRAM_BASE_S "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address") +set(MPC_QSPI_BASE_S "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address") +set(MPC_DDR4_BASE_S "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address") + +################################################################################################### +# IRQ numbers # +################################################################################################### +set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt") +set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ") +set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt ") +set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ") +set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ") +set(TIMER2_IRQn " 5" CACHE STRING " TIMER 2 Interrupt ") +set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ") +set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ") +set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ") +set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ") +set(MGMT_PPU_IRQn "14" CACHE STRING " MGMT_PPU" ) +set(SYS_PPU_IRQn "15" CACHE STRING " SYS_PPU" ) +set(CPU0_PPU_IRQn "16" CACHE STRING " CPU0_PPU" ) +set(DEBUG_PPU_IRQn "26" CACHE STRING " DEBUG_PPU" ) +set(TIMER3_AON_IRQn "27" CACHE STRING " TIMER3_AON" ) +set(CPU0CTIIQ0_IRQn "28" CACHE STRING " CPU0CTIIQ0" ) +set(CPU0CTIIQ01_IRQn "29" CACHE STRING " CPU0CTIIQ01" ) + +set(SYS_TSTAMP_COUNTER_IRQn "32" CACHE STRING " System timestamp counter interrupt ") +set(UARTRX0_IRQn "33" CACHE STRING " UART 0 RX Interrupt ") +set(UARTTX0_IRQn "34" CACHE STRING " UART 0 TX Interrupt ") +set(UARTRX1_IRQn "35" CACHE STRING " UART 1 RX Interrupt ") +set(UARTTX1_IRQn "36" CACHE STRING " UART 1 TX Interrupt ") +set(UARTRX2_IRQn "37" CACHE STRING " UART 2 RX Interrupt ") +set(UARTTX2_IRQn "38" CACHE STRING " UART 2 TX Interrupt ") +set(UARTRX3_IRQn "39" CACHE STRING " UART 3 RX Interrupt ") +set(UARTTX3_IRQn "40" CACHE STRING " UART 3 TX Interrupt ") +set(UARTRX4_IRQn "41" CACHE STRING " UART 4 RX Interrupt ") +set(UARTTX4_IRQn "42" CACHE STRING " UART 4 TX Interrupt ") +set(UART0_IRQn "43" CACHE STRING " UART 0 combined Interrupt ") +set(UART1_IRQn "44" CACHE STRING " UART 1 combined Interrupt ") +set(UART2_IRQn "45" CACHE STRING " UART 2 combined Interrupt ") +set(UART3_IRQn "46" CACHE STRING " UART 3 combined Interrupt ") +set(UART4_IRQn "47" CACHE STRING " UART 4 combined Interrupt ") +set(UARTOVF_IRQn "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ") +set(ETHERNET_IRQn "49" CACHE STRING " Ethernet Interrupt ") +set(I2S_IRQn "50" CACHE STRING " Audio I2S Interrupt ") +set(TSC_IRQn "51" CACHE STRING " Touch Screen Interrupt ") +set(USB_IRQn "52" CACHE STRING " USB Interrupt ") +set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt ") +set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ") +set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ") + +if (ETHOS_U_NPU_ENABLED) +set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ") +endif () + +set(GPIO0_IRQn "69" CACHE STRING " GPIO 0 Combined Interrupt ") +set(GPIO1_IRQn "70" CACHE STRING " GPIO 1 Combined Interrupt ") +set(GPIO2_IRQn "71" CACHE STRING " GPIO 2 Combined Interrupt ") +set(GPIO3_IRQn "72" CACHE STRING " GPIO 3 Combined Interrupt ") +set(GPIO0_0_IRQn "73" CACHE STRING "") +set(GPIO0_1_IRQn "74" CACHE STRING "") +set(GPIO0_2_IRQn "75" CACHE STRING "") +set(GPIO0_3_IRQn "76" CACHE STRING "") +set(GPIO0_4_IRQn "77" CACHE STRING "") +set(GPIO0_5_IRQn "78" CACHE STRING "") +set(GPIO0_6_IRQn "79" CACHE STRING "") +set(GPIO0_7_IRQn "80" CACHE STRING "") +set(GPIO0_8_IRQn "81" CACHE STRING "") +set(GPIO0_9_IRQn "82" CACHE STRING "") +set(GPIO0_10_IRQn "83" CACHE STRING "") +set(GPIO0_11_IRQn "84" CACHE STRING "") +set(GPIO0_12_IRQn "85" CACHE STRING "") +set(GPIO0_13_IRQn "86" CACHE STRING "") +set(GPIO0_14_IRQn "87" CACHE STRING "") +set(GPIO0_15_IRQn "88" CACHE STRING "") +set(GPIO1_0_IRQn "89" CACHE STRING "") +set(GPIO1_1_IRQn "90" CACHE STRING "") +set(GPIO1_2_IRQn "91" CACHE STRING "") +set(GPIO1_3_IRQn "92" CACHE STRING "") +set(GPIO1_4_IRQn "93" CACHE STRING "") +set(GPIO1_5_IRQn "94" CACHE STRING "") +set(GPIO1_6_IRQn "95" CACHE STRING "") +set(GPIO1_7_IRQn "96" CACHE STRING "") +set(GPIO1_8_IRQn "97" CACHE STRING "") +set(GPIO1_9_IRQn "98" CACHE STRING "") +set(GPIO1_10_IRQn "99" CACHE STRING "") +set(GPIO1_11_IRQn "100" CACHE STRING "") +set(GPIO1_12_IRQn "101" CACHE STRING "") +set(GPIO1_13_IRQn "102" CACHE STRING "") +set(GPIO1_14_IRQn "103" CACHE STRING "") +set(GPIO1_15_IRQn "104" CACHE STRING "") +set(GPIO2_0_IRQn "105" CACHE STRING "") +set(GPIO2_1_IRQn "106" CACHE STRING "") +set(GPIO2_2_IRQn "107" CACHE STRING "") +set(GPIO2_3_IRQn "108" CACHE STRING "") +set(GPIO2_4_IRQn "109" CACHE STRING "") +set(GPIO2_5_IRQn "110" CACHE STRING "") +set(GPIO2_6_IRQn "111" CACHE STRING "") +set(GPIO2_7_IRQn "112" CACHE STRING "") +set(GPIO2_8_IRQn "113" CACHE STRING "") +set(GPIO2_9_IRQn "114" CACHE STRING "") +set(GPIO2_10_IRQn "115" CACHE STRING "") +set(GPIO2_11_IRQn "116" CACHE STRING "") +set(GPIO2_12_IRQn "117" CACHE STRING "") +set(GPIO2_13_IRQn "118" CACHE STRING "") +set(GPIO2_14_IRQn "119" CACHE STRING "") +set(GPIO2_15_IRQn "120" CACHE STRING "") +set(GPIO3_0_IRQn "121" CACHE STRING "") +set(GPIO3_1_IRQn "122" CACHE STRING "") +set(GPIO3_2_IRQn "123" CACHE STRING "") +set(GPIO3_3_IRQn "124" CACHE STRING "") +set(UARTRX5_IRQn "125" CACHE STRING "UART 5 RX Interrupt") +set(UARTTX5_IRQn "126" CACHE STRING "UART 5 TX Interrupt") +set(UART5_IRQn "127" CACHE STRING "UART 5 combined Interrupt") diff --git a/source/hal/platform/mps3/cmake/templates/mem_regions.h.template b/source/hal/platform/mps3/cmake/templates/mem_regions.h.template new file mode 100644 index 0000000..72978ce --- /dev/null +++ b/source/hal/platform/mps3/cmake/templates/mem_regions.h.template @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef MEM_REGION_DEFS_H +#define MEM_REGION_DEFS_H + +#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */ +#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */ +#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */ +#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */ +#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */ +#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */ +#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */ + +#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */ +#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */ +#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */ +#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */ +#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */ +#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */ +#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */ +#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */ +#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */ +#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */ +#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */ + +#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */ +#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */ +#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */ +#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */ +#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */ +#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */ +#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */ +#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */ +#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */ +#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */ + +#endif /* MEM_REGION_DEFS_H */ diff --git a/source/hal/platform/mps3/cmake/templates/peripheral_irqs.h.template b/source/hal/platform/mps3/cmake/templates/peripheral_irqs.h.template new file mode 100644 index 0000000..7696e13 --- /dev/null +++ b/source/hal/platform/mps3/cmake/templates/peripheral_irqs.h.template @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_IRQS_H +#define PERIPHERAL_IRQS_H + +/******************************************************************************/ +/* Peripheral interrupt numbers */ +/******************************************************************************/ + +/* ------------------- Cortex-M Processor Exceptions Numbers -------------- */ +/* -14 to -1 should be defined by the system header */ +/* ---------------------- Core Specific Interrupt Numbers ------------------*/ +#cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@) /* Non-Secure Watchdog Reset Interrupt */ +#cmakedefine NONSEC_WATCHDOG_IRQn (@NONSEC_WATCHDOG_IRQn@) /* Non-Secure Watchdog Interrupt */ +#cmakedefine S32K_TIMER_IRQn (@S32K_TIMER_IRQn@) /* S32K Timer Interrupt */ +#cmakedefine TIMER0_IRQn (@TIMER0_IRQn@) /* TIMER 0 Interrupt */ +#cmakedefine TIMER1_IRQn (@TIMER1_IRQn@) /* TIMER 1 Interrupt */ +#cmakedefine TIMER2_IRQn (@TIMER2_IRQn@) /* TIMER 2 Interrupt */ +#cmakedefine MPC_IRQn (@MPC_IRQn@) /* MPC Combined (@Secure@) Interrupt */ +#cmakedefine PPC_IRQn (@PPC_IRQn@) /* PPC Combined (@Secure@) Interrupt */ +#cmakedefine MSC_IRQn (@MSC_IRQn@) /* MSC Combined (@Secure@) Interrput */ +#cmakedefine BRIDGE_ERROR_IRQn (@BRIDGE_ERROR_IRQn@) /* Bridge Error Combined (@Secure@) Interrupt */ +#cmakedefine MGMT_PPU_IRQn (@MGMT_PPU_IRQn@) /* MGMT_PPU */ +#cmakedefine SYS_PPU_IRQn (@SYS_PPU_IRQn@) /* SYS_PPU */ +#cmakedefine CPU0_PPU_IRQn (@CPU0_PPU_IRQn@) /* CPU0_PPU */ +#cmakedefine DEBUG_PPU_IRQn (@DEBUG_PPU_IRQn@) /* DEBUG_PPU */ +#cmakedefine TIMER3_AON_IRQn (@TIMER3_AON_IRQn@) /* TIMER3_AON */ +#cmakedefine CPU0CTIIQ0_IRQn (@CPU0CTIIQ0_IRQn@) /* CPU0CTIIQ0 */ +#cmakedefine CPU0CTIIQ01_IRQn (@CPU0CTIIQ01_IRQn@) /* CPU0CTIIQ01 */ + +#cmakedefine SYS_TSTAMP_COUNTER_IRQn (@SYS_TSTAMP_COUNTER_IRQn@) /* System timestamp counter interrupt */ + +/* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */ +#cmakedefine UARTRX0_IRQn (@UARTRX0_IRQn@) /* UART 0 RX Interrupt */ +#cmakedefine UARTTX0_IRQn (@UARTTX0_IRQn@) /* UART 0 TX Interrupt */ +#cmakedefine UARTRX1_IRQn (@UARTRX1_IRQn@) /* UART 1 RX Interrupt */ +#cmakedefine UARTTX1_IRQn (@UARTTX1_IRQn@) /* UART 1 TX Interrupt */ +#cmakedefine UARTRX2_IRQn (@UARTRX2_IRQn@) /* UART 2 RX Interrupt */ +#cmakedefine UARTTX2_IRQn (@UARTTX2_IRQn@) /* UART 2 TX Interrupt */ +#cmakedefine UARTRX3_IRQn (@UARTRX3_IRQn@) /* UART 3 RX Interrupt */ +#cmakedefine UARTTX3_IRQn (@UARTTX3_IRQn@) /* UART 3 TX Interrupt */ +#cmakedefine UARTRX4_IRQn (@UARTRX4_IRQn@) /* UART 4 RX Interrupt */ +#cmakedefine UARTTX4_IRQn (@UARTTX4_IRQn@) /* UART 4 TX Interrupt */ +#cmakedefine UART0_IRQn (@UART0_IRQn@) /* UART 0 combined Interrupt */ +#cmakedefine UART1_IRQn (@UART1_IRQn@) /* UART 1 combined Interrupt */ +#cmakedefine UART2_IRQn (@UART2_IRQn@) /* UART 2 combined Interrupt */ +#cmakedefine UART3_IRQn (@UART3_IRQn@) /* UART 3 combined Interrupt */ +#cmakedefine UART4_IRQn (@UART4_IRQn@) /* UART 4 combined Interrupt */ +#cmakedefine UARTOVF_IRQn (@UARTOVF_IRQn@) /* UART 0,1,2,3 and 4 Overflow Interrupt */ +#cmakedefine ETHERNET_IRQn (@ETHERNET_IRQn@) /* Ethernet Interrupt */ +#cmakedefine I2S_IRQn (@I2S_IRQn@) /* I2S Interrupt */ +#cmakedefine TSC_IRQn (@TSC_IRQn@) /* Touch Screen Interrupt */ +#cmakedefine SPI2_IRQn (@SPI2_IRQn@) /* SPI 2 Interrupt */ +#cmakedefine SPI3_IRQn (@SPI3_IRQn@) /* SPI 3 Interrupt */ +#cmakedefine SPI4_IRQn (@SPI4_IRQn@) /* SPI 4 Interrupt */ + +#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */ + +#cmakedefine GPIO0_IRQn (@GPIO0_IRQn@) /* GPIO 0 Combined Interrupt */ +#cmakedefine GPIO1_IRQn (@GPIO1_IRQn@) /* GPIO 1 Combined Interrupt */ +#cmakedefine GPIO2_IRQn (@GPIO2_IRQn@) /* GPIO 2 Combined Interrupt */ +#cmakedefine GPIO3_IRQn (@GPIO3_IRQn@) /* GPIO 3 Combined Interrupt */ + +#cmakedefine GPIO0_0_IRQn (@GPIO0_0_IRQn@) /* All P0 I/O pins used as irq source */ +#cmakedefine GPIO0_1_IRQn (@GPIO0_1_IRQn@) /* There are 16 pins in total */ +#cmakedefine GPIO0_2_IRQn (@GPIO0_2_IRQn@) +#cmakedefine GPIO0_3_IRQn (@GPIO0_3_IRQn@) +#cmakedefine GPIO0_4_IRQn (@GPIO0_4_IRQn@) +#cmakedefine GPIO0_5_IRQn (@GPIO0_5_IRQn@) +#cmakedefine GPIO0_6_IRQn (@GPIO0_6_IRQn@) +#cmakedefine GPIO0_7_IRQn (@GPIO0_7_IRQn@) +#cmakedefine GPIO0_8_IRQn (@GPIO0_8_IRQn@) +#cmakedefine GPIO0_9_IRQn (@GPIO0_9_IRQn@) +#cmakedefine GPIO0_10_IRQn (@GPIO0_10_IRQn@) +#cmakedefine GPIO0_11_IRQn (@GPIO0_11_IRQn@) +#cmakedefine GPIO0_12_IRQn (@GPIO0_12_IRQn@) +#cmakedefine GPIO0_13_IRQn (@GPIO0_13_IRQn@) +#cmakedefine GPIO0_14_IRQn (@GPIO0_14_IRQn@) +#cmakedefine GPIO0_15_IRQn (@GPIO0_15_IRQn@) +#cmakedefine GPIO1_0_IRQn (@GPIO1_0_IRQn@) /* All P1 I/O pins used as irq source */ +#cmakedefine GPIO1_1_IRQn (@GPIO1_1_IRQn@) /* There are 16 pins in total */ +#cmakedefine GPIO1_2_IRQn (@GPIO1_2_IRQn@) +#cmakedefine GPIO1_3_IRQn (@GPIO1_3_IRQn@) +#cmakedefine GPIO1_4_IRQn (@GPIO1_4_IRQn@) +#cmakedefine GPIO1_5_IRQn (@GPIO1_5_IRQn@) +#cmakedefine GPIO1_6_IRQn (@GPIO1_6_IRQn@) +#cmakedefine GPIO1_7_IRQn (@GPIO1_7_IRQn@) +#cmakedefine GPIO1_8_IRQn (@GPIO1_8_IRQn@) +#cmakedefine GPIO1_9_IRQn (@GPIO1_9_IRQn@) +#cmakedefine GPIO1_10_IRQn (@GPIO1_10_IRQn@) +#cmakedefine GPIO1_11_IRQn (@GPIO1_11_IRQn@) +#cmakedefine GPIO1_12_IRQn (@GPIO1_12_IRQn@) +#cmakedefine GPIO1_13_IRQn (@GPIO1_13_IRQn@) +#cmakedefine GPIO1_14_IRQn (@GPIO1_14_IRQn@) +#cmakedefine GPIO1_15_IRQn (@GPIO1_15_IRQn@) +#cmakedefine GPIO2_0_IRQn (@GPIO2_0_IRQn@) /* All P2 I/O pins used as irq source */ +#cmakedefine GPIO2_1_IRQn (@GPIO2_1_IRQn@) /* There are 15 pins in total */ +#cmakedefine GPIO2_2_IRQn (@GPIO2_2_IRQn@) +#cmakedefine GPIO2_3_IRQn (@GPIO2_3_IRQn@) +#cmakedefine GPIO2_4_IRQn (@GPIO2_4_IRQn@) +#cmakedefine GPIO2_5_IRQn (@GPIO2_5_IRQn@) +#cmakedefine GPIO2_6_IRQn (@GPIO2_6_IRQn@) +#cmakedefine GPIO2_7_IRQn (@GPIO2_7_IRQn@) +#cmakedefine GPIO2_8_IRQn (@GPIO2_8_IRQn@) +#cmakedefine GPIO2_9_IRQn (@GPIO2_9_IRQn@) +#cmakedefine GPIO2_10_IRQn (@GPIO2_10_IRQn@) +#cmakedefine GPIO2_11_IRQn (@GPIO2_11_IRQn@) +#cmakedefine GPIO2_12_IRQn (@GPIO2_12_IRQn@) +#cmakedefine GPIO2_13_IRQn (@GPIO2_13_IRQn@) +#cmakedefine GPIO2_14_IRQn (@GPIO2_14_IRQn@) +#cmakedefine GPIO2_15_IRQn (@GPIO2_15_IRQn@) +#cmakedefine GPIO3_0_IRQn (@GPIO3_0_IRQn@) /* All P3 I/O pins used as irq source */ +#cmakedefine GPIO3_1_IRQn (@GPIO3_1_IRQn@) /* There are 4 pins in total */ +#cmakedefine GPIO3_2_IRQn (@GPIO3_2_IRQn@) +#cmakedefine GPIO3_3_IRQn (@GPIO3_3_IRQn@) +#cmakedefine UARTRX5_IRQn (@UARTRX5_IRQn@) /* UART 5 RX Interrupt */ +#cmakedefine UARTTX5_IRQn (@UARTTX5_IRQn@) /* UART 5 TX Interrupt */ +#cmakedefine UART5_IRQn (@UART5_IRQn@) /* UART 5 combined Interrupt */ +#cmakedefine HDCLCD_IRQn (@HDCLCD_IRQn@) /* HDCLCD Interrupt */ + +#endif /* PERIPHERAL_IRQS_H */ diff --git a/source/hal/platform/mps3/cmake/templates/peripheral_memmap.h.template b/source/hal/platform/mps3/cmake/templates/peripheral_memmap.h.template new file mode 100644 index 0000000..d7f0b3a --- /dev/null +++ b/source/hal/platform/mps3/cmake/templates/peripheral_memmap.h.template @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_MEMMAP_H +#define PERIPHERAL_MEMMAP_H + +#cmakedefine DESIGN_NAME "@DESIGN_NAME@" + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +#cmakedefine CMSDK_GPIO0_BASE (@CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */ +#cmakedefine CMSDK_GPIO1_BASE (@CMSDK_GPIO1_BASE@) /* User GPIO 1 Base Address */ +#cmakedefine CMSDK_GPIO2_BASE (@CMSDK_GPIO2_BASE@) /* User GPIO 2 Base Address */ +#cmakedefine CMSDK_GPIO3_BASE (@CMSDK_GPIO3_BASE@) /* User GPIO 3 Base Address */ + +#cmakedefine FMC_CMDSK_GPIO_BASE0 (@FMC_CMDSK_GPIO_BASE0@) /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */ +#cmakedefine FMC_CMDSK_GPIO_BASE1 (@FMC_CMDSK_GPIO_BASE1@) /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/ +#cmakedefine FMC_CMDSK_GPIO_BASE2 (@FMC_CMDSK_GPIO_BASE2@) /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/ +#cmakedefine FMC_USER_AHB_BASE (@FMC_USER_AHB_BASE@) /* FMC_USER_AHB_BASE Base Address (4KB)*/ + +#cmakedefine DMA0_BASE (@DMA0_BASE@) /* DMA0 (4KB) */ +#cmakedefine DMA1_BASE (@DMA1_BASE@) /* DMA1 (4KB) */ +#cmakedefine DMA2_BASE (@DMA2_BASE@) /* DMA2 (4KB) */ +#cmakedefine DMA3_BASE (@DMA3_BASE@) /* DMA3 (4KB) */ + +#cmakedefine USER_APB0_BASE (@USER_APB0_BASE@) /* User APB0 */ +#cmakedefine USER_APB1_BASE (@USER_APB1_BASE@) /* User APB1 */ +#cmakedefine USER_APB2_BASE (@USER_APB2_BASE@) /* User APB2 */ +#cmakedefine USER_APB3_BASE (@USER_APB3_BASE@) /* User APB3 */ + +#cmakedefine MPS3_I2C0_BASE (@MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */ +#cmakedefine MPS3_I2C1_BASE (@MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */ +#cmakedefine MPS3_SSP2_BASE (@MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */ +#cmakedefine MPS3_SSP3_BASE (@MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */ + +#cmakedefine MPS3_SSP4_BASE (@MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */ +#cmakedefine MPS3_I2C2_BASE (@MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */ +#cmakedefine MPS3_I2C3_BASE (@MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */ + +#cmakedefine USER_APB_BASE (@USER_APB_BASE@) /* User APB Base Address */ +#cmakedefine MPS3_I2C4_BASE (@MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */ +#cmakedefine MPS3_I2C5_BASE (@MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */ +#cmakedefine MPS3_SCC_BASE (@MPS3_SCC_BASE@) /* SCC Base Address */ +#cmakedefine MPS3_AAIC_I2S_BASE (@MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */ +#cmakedefine MPS3_FPGAIO_BASE (@MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */ +#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */ +#cmakedefine CMSDK_UART0_BASE (@CMSDK_UART0_BASE@) /* UART 0 Base Address */ +#cmakedefine CMSDK_UART1_BASE (@CMSDK_UART1_BASE@) /* UART 1 Base Address */ +#cmakedefine CMSDK_UART2_BASE (@CMSDK_UART2_BASE@) /* UART 2 Base Address */ +#cmakedefine CMSDK_UART3_BASE (@CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/ + +#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +#cmakedefine CMSDK_UART4_BASE (@CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/ +#cmakedefine CMSDK_UART5_BASE (@CMSDK_UART5_BASE@) /* UART 5 Base Address */ +#cmakedefine HDMI_AUDIO_BASE (@HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */ +#cmakedefine CLCD_CONFIG_BASE (@CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */ +#cmakedefine RTC_BASE (@RTC_BASE@) /* RTC Base address */ +#cmakedefine SMSC9220_BASE (@SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */ +#cmakedefine USB_BASE (@USB_BASE@) /* USB Base Address */ +#cmakedefine CMSDK_SDIO_BASE (@CMSDK_SDIO_BASE@) /* User SDIO Base Address */ +#cmakedefine MPS3_CLCD_BASE (@MPS3_CLCD_BASE@) /* HDLCD Base Address */ +#cmakedefine MPS3_eMMC_BASE (@MPS3_eMMC_BASE@) /* User eMMC Base Address */ +#cmakedefine USER_BASE (@USER_BASE@) /* User ? Base Address */ + +#cmakedefine QSPI_XIP_BASE (@QSPI_XIP_BASE@) /* QSPI XIP config Base Address */ +#cmakedefine QSPI_WRITE_BASE (@QSPI_WRITE_BASE@) /* QSPI write config Base Address */ + +/******************************************************************************/ +/* Secure Peripheral memory map */ +/******************************************************************************/ + +#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* ISRAM0 Memory Protection Controller Secure base address */ +#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* ISRAM1 Memory Protection Controller Secure base address */ + +#cmakedefine SEC_CMSDK_GPIO0_BASE (@SEC_CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */ +#cmakedefine SEC_CMSDK_GPIO1_BASE (@SEC_CMSDK_GPIO1_BASE@) /* User GPIO 0 Base Address */ +#cmakedefine SEC_CMSDK_GPIO2_BASE (@SEC_CMSDK_GPIO2_BASE@) /* User GPIO 0 Base Address */ +#cmakedefine SEC_CMSDK_GPIO3_BASE (@SEC_CMSDK_GPIO3_BASE@) /* User GPIO 0 Base Address */ + +#cmakedefine SEC_AHB_USER0_BASE (@SEC_AHB_USER0_BASE@) /* AHB USER 0 Base Address (4KB) */ +#cmakedefine SEC_AHB_USER1_BASE (@SEC_AHB_USER1_BASE@) /* AHB USER 1 Base Address (4KB)*/ +#cmakedefine SEC_AHB_USER2_BASE (@SEC_AHB_USER2_BASE@) /* AHB USER 2 Base Address (4KB)*/ +#cmakedefine SEC_AHB_USER3_BASE (@SEC_AHB_USER3_BASE@) /* AHB USER 3 Base Address (4KB)*/ + +#cmakedefine SEC_DMA0_BASE (@SEC_DMA0_BASE@) /* DMA0 (4KB) */ +#cmakedefine SEC_DMA1_BASE (@SEC_DMA1_BASE@) /* DMA1 (4KB) */ +#cmakedefine SEC_DMA2_BASE (@SEC_DMA2_BASE@) /* DMA2 (4KB) */ +#cmakedefine SEC_DMA3_BASE (@SEC_DMA3_BASE@) /* DMA3 (4KB) */ + +#cmakedefine SEC_USER_APB0_BASE (@SEC_USER_APB0_BASE@) /* User APB0 */ +#cmakedefine SEC_USER_APB1_BASE (@SEC_USER_APB1_BASE@) /* User APB1 */ +#cmakedefine SEC_USER_APB2_BASE (@SEC_USER_APB2_BASE@) /* User APB2 */ +#cmakedefine SEC_USER_APB3_BASE (@SEC_USER_APB3_BASE@) /* User APB3 */ + +#cmakedefine SEC_MPS3_I2C0_BASE (@SEC_MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */ +#cmakedefine SEC_MPS3_I2C1_BASE (@SEC_MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */ +#cmakedefine SEC_MPS3_SSP2_BASE (@SEC_MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */ +#cmakedefine SEC_MPS3_SSP3_BASE (@SEC_MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */ + +#cmakedefine SEC_MPS3_SSP4_BASE (@SEC_MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */ +#cmakedefine SEC_MPS3_I2C2_BASE (@SEC_MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */ +#cmakedefine SEC_MPS3_I2C3_BASE (@SEC_MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */ + +#cmakedefine SEC_MPS3_I2C4_BASE (@SEC_MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */ +#cmakedefine SEC_MPS3_I2C5_BASE (@SEC_MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */ +#cmakedefine SEC_MPS3_SCC_BASE (@SEC_MPS3_SCC_BASE@) /* SCC Base Address */ +#cmakedefine SEC_MPS3_AAIC_I2S_BASE (@SEC_MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */ +#cmakedefine SEC_MPS3_FPGAIO_BASE (@SEC_MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */ +#cmakedefine SEC_CMSDK_UART0_BASE (@SEC_CMSDK_UART0_BASE@) /* UART 0 Base Address */ +#cmakedefine SEC_CMSDK_UART1_BASE (@SEC_CMSDK_UART1_BASE@) /* UART 1 Base Address */ +#cmakedefine SEC_CMSDK_UART2_BASE (@SEC_CMSDK_UART2_BASE@) /* UART 2 Base Address */ +#cmakedefine SEC_CMSDK_UART3_BASE (@SEC_CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/ + +#cmakedefine SEC_CMSDK_UART4_BASE (@SEC_CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/ +#cmakedefine SEC_CMSDK_UART5_BASE (@SEC_CMSDK_UART5_BASE@) /* UART 5 Base Address */ +#cmakedefine SEC_HDMI_AUDIO_BASE (@SEC_HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */ +#cmakedefine SEC_CLCD_CONFIG_BASE (@SEC_CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */ +#cmakedefine SEC_RTC_BASE (@SEC_RTC_BASE@) /* RTC Base address */ +#cmakedefine SEC_SMSC9220_BASE (@SEC_SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */ +#cmakedefine SEC_USB_BASE (@SEC_USB_BASE@) /* USB Base Address */ + +#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +#cmakedefine SEC_USER_BASE (@SEC_USER_BASE@) /* User ? Base Address */ + +#cmakedefine SEC_QSPI_XIP_BASE (@SEC_QSPI_XIP_BASE@) /* QSPI XIP config Base Address */ +#cmakedefine SEC_QSPI_WRITE_BASE (@SEC_QSPI_WRITE_BASE@) /* QSPI write config Base Address */ + +/******************************************************************************/ +/* MPCs */ +/******************************************************************************/ + +#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* Internal SRAM 0 MPC */ +#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* Internal SRAM 1 MPC */ +#cmakedefine MPC_BRAM_BASE_S (@MPC_BRAM_BASE_S@) /* SRAM Memory Protection Controller Secure base address */ +#cmakedefine MPC_QSPI_BASE_S (@MPC_QSPI_BASE_S@) /* QSPI Memory Protection Controller Secure base address */ +#cmakedefine MPC_DDR4_BASE_S (@MPC_DDR4_BASE_S@) /* DDR4 Memory Protection Controller Secure base address */ + +#endif /* PERIPHERAL_MEMMAP_H */ diff --git a/source/hal/platform/mps3/cmake/templates/timing_adapter_settings.template b/source/hal/platform/mps3/cmake/templates/timing_adapter_settings.template new file mode 100644 index 0000000..d5e202a --- /dev/null +++ b/source/hal/platform/mps3/cmake/templates/timing_adapter_settings.template @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef TIMING_ADAPTER_SETTINGS_H +#define TIMING_ADAPTER_SETTINGS_H + +#cmakedefine TA0_BASE (@TA0_BASE@) +#cmakedefine TA1_BASE (@TA1_BASE@) + +/* Timing adapter settings for AXI0 */ +#if defined(TA0_BASE) + +#define TA0_MAXR (@TA0_MAXR@) +#define TA0_MAXW (@TA0_MAXW@) +#define TA0_MAXRW (@TA0_MAXRW@) +#define TA0_RLATENCY (@TA0_RLATENCY@) +#define TA0_WLATENCY (@TA0_WLATENCY@) +#define TA0_PULSE_ON (@TA0_PULSE_ON@) +#define TA0_PULSE_OFF (@TA0_PULSE_OFF@) +#define TA0_BWCAP (@TA0_BWCAP@) +#define TA0_PERFCTRL (@TA0_PERFCTRL@) +#define TA0_PERFCNT (@TA0_PERFCNT@) +#define TA0_MODE (@TA0_MODE@) +#define TA0_HISTBIN (@TA0_HISTBIN@) +#define TA0_HISTCNT (@TA0_HISTCNT@) + +#endif /* defined(TA0_BASE) */ + +/* Timing adapter settings for AXI1 */ +#if defined(TA1_BASE) + +#define TA1_MAXR (@TA1_MAXR@) +#define TA1_MAXW (@TA1_MAXW@) +#define TA1_MAXRW (@TA1_MAXRW@) +#define TA1_RLATENCY (@TA1_RLATENCY@) +#define TA1_WLATENCY (@TA1_WLATENCY@) +#define TA1_PULSE_ON (@TA1_PULSE_ON@) +#define TA1_PULSE_OFF (@TA1_PULSE_OFF@) +#define TA1_BWCAP (@TA1_BWCAP@) +#define TA1_PERFCTRL (@TA1_PERFCTRL@) +#define TA1_PERFCNT (@TA1_PERFCNT@) +#define TA1_MODE (@TA1_MODE@) +#define TA1_HISTBIN (@TA1_HISTBIN@) +#define TA1_HISTCNT (@TA1_HISTCNT@) + +#endif /* defined(TA1_BASE) */ + +#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h b/source/hal/platform/mps3/include/device_mps3.h index e0dea1b..e0dea1b 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h +++ b/source/hal/platform/mps3/include/device_mps3.h diff --git a/source/application/hal/platforms/bare-metal/bsp/include/bsp.h b/source/hal/platform/mps3/include/platform_drivers.h index 2bd4fa1..c5ed561 100644 --- a/source/application/hal/platforms/bare-metal/bsp/include/bsp.h +++ b/source/hal/platform/mps3/include/platform_drivers.h @@ -14,29 +14,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef BSP_H -#define BSP_H -/* Core modules - these are common */ -#include "bsp_core_log.h" /* Logging related helpers. */ -#include "uart_stdout.h" /* stdout over UART. */ - -#if defined(MPS3_PLATFORM) /* If running on MPS3 platform. */ +#ifndef PLATFORM_DRIVER_H +#define PLATFORM_DRIVER_H +#include "log_macros.h" /* Logging related helpers. */ +#include "uart_stdout.h" /* stdout over UART. */ #include "smm_mps3.h" /* Mem map for MPS3 peripherals. */ #include "glcd_mps3.h" /* LCD functions. */ #include "timer_mps3.h" /* Timer functions. */ #include "device_mps3.h" /* FPGA level definitions and functions. */ +#include "peripheral_irqs.h"/* IRQ numbers for this platform */ -#else /* MPS3_PLATFORM */ - -#include "stubs_simple_platform.h" /* Stubs for simple_platform. */ -#include "timer_simple_platform.h" /* Timer API for simple_platform. */ - -#endif /* MPS3_PLATFORM */ - -#if defined(ARM_NPU) -#include "ethosu_mem_config.h" -#endif /* defined(ARM_NPU) */ - -#endif /* BSP_H */ +#endif /* PLATFORM_DRIVER_H */ diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/smm_mps3.h b/source/hal/platform/mps3/include/smm_mps3.h index 1c0e0f2..1c0e0f2 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/smm_mps3.h +++ b/source/hal/platform/mps3/include/smm_mps3.h diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/timer_mps3.h b/source/hal/platform/mps3/include/timer_mps3.h index 14d64e5..70d059c 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/timer_mps3.h +++ b/source/hal/platform/mps3/include/timer_mps3.h @@ -30,7 +30,7 @@ typedef struct _mps3_time_counter { /* Running at processor core's internal clock rate, triggered by SysTick. */ uint64_t counter_systick; -} mps3_time_counter; +} base_time_counter; /** * @brief Resets the counters. @@ -41,36 +41,36 @@ void timer_reset(void); * @brief Gets the current counter values. * @returns Mps3 timer counter. **/ -mps3_time_counter get_time_counter(void); +base_time_counter get_time_counter(void); /** * @brief Gets the duration elapsed between two counters in milliseconds. - * @param[in] start Pointer to mps3_time_counter value at start time. - * @param[in] end Pointer to mps3_time_counter value at end. + * @param[in] start Pointer to base_time_counter value at start time. + * @param[in] end Pointer to base_time_counter value at end. * @returns Difference in milliseconds between the two give counters * expressed as an unsigned integer. **/ -uint32_t get_duration_milliseconds(mps3_time_counter *start, - mps3_time_counter *end); +uint32_t get_duration_milliseconds(base_time_counter *start, + base_time_counter *end); /** * @brief Gets the duration elapsed between two counters in microseconds. - * @param[in] start Pointer to mps3_time_counter value at start time. - * @param[in] end Pointer to mps3_time_counter value at end. + * @param[in] start Pointer to base_time_counter value at start time. + * @param[in] end Pointer to base_time_counter value at end. * @returns Difference in microseconds between the two give counters * expressed as an unsigned integer. **/ -uint32_t get_duration_microseconds(mps3_time_counter *start, - mps3_time_counter *end); +uint32_t get_duration_microseconds(base_time_counter *start, + base_time_counter *end); /** * @brief Gets the cycle counts elapsed between start and end. - * @param[in] start Pointer to mps3_time_counter value at start time. - * @param[in] end Pointer to mps3_time_counter value at end. + * @param[in] start Pointer to base_time_counter value at start time. + * @param[in] end Pointer to base_time_counter value at end. * @return Difference in counter values as 32 bit unsigned integer. **/ -uint64_t get_cycle_count_diff(mps3_time_counter *start, - mps3_time_counter *end); +uint64_t get_cycle_count_diff(base_time_counter *start, + base_time_counter *end); /** * @brief Enables or triggers cycle counting mechanism, if required diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c b/source/hal/platform/mps3/source/device_mps3.c index 9a923c7..fa57c2e 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c +++ b/source/hal/platform/mps3/source/device_mps3.c @@ -16,7 +16,7 @@ */ #include "device_mps3.h" -#include "bsp_core_log.h" +#include "log_macros.h" #include "smm_mps3.h" #include <inttypes.h> diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c b/source/hal/platform/mps3/source/timer_mps3.c index c0c3bdf..9b8914c 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/timer_mps3.c +++ b/source/hal/platform/mps3/source/timer_mps3.c @@ -16,7 +16,7 @@ */ #include "timer_mps3.h" -#include "bsp_core_log.h" +#include "log_macros.h" #include "device_mps3.h" #include <inttypes.h> @@ -33,9 +33,9 @@ void timer_reset(void) debug("system tick config ready\n"); } -mps3_time_counter get_time_counter(void) +base_time_counter get_time_counter(void) { - mps3_time_counter t = { + base_time_counter t = { .counter_1Hz = MPS3_FPGAIO->CLK1HZ, .counter_100Hz = MPS3_FPGAIO->CLK100HZ, .counter_fpga = MPS3_FPGAIO->COUNTER, @@ -54,8 +54,8 @@ mps3_time_counter get_time_counter(void) * the time elapsed has been big (in days) this could happen and is currently * not handled. **/ -uint32_t get_duration_milliseconds(mps3_time_counter *start, - mps3_time_counter *end) +uint32_t get_duration_milliseconds(base_time_counter *start, + base_time_counter *end) { uint32_t time_elapsed = 0; if (end->counter_100Hz > start->counter_100Hz) { @@ -79,8 +79,8 @@ uint32_t get_duration_milliseconds(mps3_time_counter *start, * Like the microsecond counterpart, this function could return wrong results when * the counter (MAINCLK) overflows. There are no overflow counters available. **/ -uint32_t get_duration_microseconds(mps3_time_counter *start, - mps3_time_counter *end) +uint32_t get_duration_microseconds(base_time_counter *start, + base_time_counter *end) { const int divisor = GetMPS3CoreClock()/1000000; uint32_t time_elapsed = 0; @@ -93,8 +93,8 @@ uint32_t get_duration_microseconds(mps3_time_counter *start, return time_elapsed; } -uint64_t get_cycle_count_diff(mps3_time_counter *start, - mps3_time_counter *end) +uint64_t get_cycle_count_diff(base_time_counter *start, + base_time_counter *end) { if (start->counter_systick > end->counter_systick) { warn("start > end; counter might have overflown\n"); diff --git a/source/hal/platform/simple/CMakeLists.txt b/source/hal/platform/simple/CMakeLists.txt new file mode 100644 index 0000000..cd3a2bc --- /dev/null +++ b/source/hal/platform/simple/CMakeLists.txt @@ -0,0 +1,100 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# A generic (simple) platform support library # +######################################################### + +cmake_minimum_required(VERSION 3.15.6) +set(PLATFORM_DRIVERS_TARGET platform-drivers) +project(${PLATFORM_DRIVERS_TARGET} + DESCRIPTION "Platform drivers library for a generic target" + LANGUAGES C CXX ASM) + +# 1. We should be cross-compiling (MPS3 taregt only runs Cortex-M targets) +if (NOT ${CMAKE_CROSSCOMPILING}) + message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.") +endif() + +# 2. Set the platform cmake descriptor file +if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE) + set(PLATFORM_CMAKE_DESCRIPTOR_FILE + ${CMAKE_CURRENT_SOURCE_DIR}/cmake/subsystem-profiles/simple_platform.cmake) +endif() + +## Include the platform cmake descriptor file +include(${PLATFORM_CMAKE_DESCRIPTOR_FILE}) + +# 3. Generate sources: +if (NOT DEFINED SOURCE_GEN_DIR) + set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp) +endif() + +set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template) +set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template) +set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template) + +configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h") +configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h") +configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h") + +# If a TA config file is provided, we generate a settings file +if (DEFINED TA_CONFIG_FILE) + include(${TA_CONFIG_FILE}) + set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/timing_adapter_settings.template) + configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h") +endif() + +# 4. Create static library +add_library(${PLATFORM_DRIVERS_TARGET} STATIC) + +## Include directories - public +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + include + ${SOURCE_GEN_DIR}) + +## Platform sources +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/stubs_glcd.c + source/timer_simple_platform.c) + +## Platform component: uart +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_pl011/uart_pl011.c) +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_pl011/include) + +## Compile defs +target_compile_definitions(${PLATFORM_DRIVERS_TARGET} + PUBLIC + ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ} + $<$<BOOL:TA_CONFIG_FILE>:TIMING_ADAPTER_AVAILABLE>) + +target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC + cmsis_device + log) + +# 6 Display status: +message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) +message(STATUS "*******************************************************") +message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake new file mode 100644 index 0000000..e6cfef3 --- /dev/null +++ b/source/hal/platform/simple/cmake/subsystem-profiles/simple_platform.cmake @@ -0,0 +1,93 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2021 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +# CMake configuration file for peripheral memory map for simple platform. This is a stripped down +# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However, +# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of +# the CMSDK UART block used by the MPS3 FPGA and FVP implementations. +################################################################################################### +# Mem sizes # +################################################################################################### +set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") +set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks") +set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB") +set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB") +set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB") +set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") + +################################################################################################### +# Base addresses for memory regions # +################################################################################################### +set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") +set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") +set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") +set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address") +set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address") +set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address") +set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address") +set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") +set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") +set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") +set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") +set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") + +set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") +set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") +set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") +set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address") +set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address") +set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address") +set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address") +set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address") +set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") +set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") +set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") +set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") + +################################################################################################### +# Application specific config # +################################################################################################### + +# This parameter is based on the linker/scatter script for simple platform. Do not change this +# parameter in isolation. +set(DESIGN_NAME "Simple platform" CACHE STRING "Design name") + +# SRAM size reserved for activation buffers +math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) + + +################################################################################################### +# Base addresses # +################################################################################################### +set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address") + +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif () + +################################################################################################### +# IRQ numbers # +################################################################################################### +if (ETHOS_U_NPU_ENABLED) + set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt") +endif () diff --git a/source/hal/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/platform/simple/cmake/templates/mem_regions.h.template new file mode 100644 index 0000000..72978ce --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/mem_regions.h.template @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef MEM_REGION_DEFS_H +#define MEM_REGION_DEFS_H + +#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */ +#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */ +#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */ +#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */ +#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */ +#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */ +#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */ + +#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */ +#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */ +#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */ +#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */ +#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */ +#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */ +#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */ +#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */ +#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */ +#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */ +#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */ +#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */ + +#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */ +#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */ +#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */ +#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */ +#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */ +#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */ +#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */ +#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */ +#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */ +#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */ +#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */ + +#endif /* MEM_REGION_DEFS_H */ diff --git a/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template new file mode 100644 index 0000000..8126cb4 --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/peripheral_irqs.h.template @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_IRQS_H +#define PERIPHERAL_IRQS_H + +/******************************************************************************/ +/* Peripheral interrupt numbers */ +/******************************************************************************/ + +#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */ + +#endif /* PERIPHERAL_IRQS_H */ diff --git a/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template new file mode 100644 index 0000000..2bfaafc --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/peripheral_memmap.h.template @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef PERIPHERAL_MEMMAP_H +#define PERIPHERAL_MEMMAP_H + +#cmakedefine DESIGN_NAME "@DESIGN_NAME@" + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */ + +#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +/******************************************************************************/ +/* Secure Peripheral memory map */ +/******************************************************************************/ + +#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ + +#endif /* PERIPHERAL_MEMMAP_H */ diff --git a/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template new file mode 100644 index 0000000..d5e202a --- /dev/null +++ b/source/hal/platform/simple/cmake/templates/timing_adapter_settings.template @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// Auto-generated file +// ** DO NOT EDIT ** + +#ifndef TIMING_ADAPTER_SETTINGS_H +#define TIMING_ADAPTER_SETTINGS_H + +#cmakedefine TA0_BASE (@TA0_BASE@) +#cmakedefine TA1_BASE (@TA1_BASE@) + +/* Timing adapter settings for AXI0 */ +#if defined(TA0_BASE) + +#define TA0_MAXR (@TA0_MAXR@) +#define TA0_MAXW (@TA0_MAXW@) +#define TA0_MAXRW (@TA0_MAXRW@) +#define TA0_RLATENCY (@TA0_RLATENCY@) +#define TA0_WLATENCY (@TA0_WLATENCY@) +#define TA0_PULSE_ON (@TA0_PULSE_ON@) +#define TA0_PULSE_OFF (@TA0_PULSE_OFF@) +#define TA0_BWCAP (@TA0_BWCAP@) +#define TA0_PERFCTRL (@TA0_PERFCTRL@) +#define TA0_PERFCNT (@TA0_PERFCNT@) +#define TA0_MODE (@TA0_MODE@) +#define TA0_HISTBIN (@TA0_HISTBIN@) +#define TA0_HISTCNT (@TA0_HISTCNT@) + +#endif /* defined(TA0_BASE) */ + +/* Timing adapter settings for AXI1 */ +#if defined(TA1_BASE) + +#define TA1_MAXR (@TA1_MAXR@) +#define TA1_MAXW (@TA1_MAXW@) +#define TA1_MAXRW (@TA1_MAXRW@) +#define TA1_RLATENCY (@TA1_RLATENCY@) +#define TA1_WLATENCY (@TA1_WLATENCY@) +#define TA1_PULSE_ON (@TA1_PULSE_ON@) +#define TA1_PULSE_OFF (@TA1_PULSE_OFF@) +#define TA1_BWCAP (@TA1_BWCAP@) +#define TA1_PERFCTRL (@TA1_PERFCTRL@) +#define TA1_PERFCNT (@TA1_PERFCNT@) +#define TA1_MODE (@TA1_MODE@) +#define TA1_HISTBIN (@TA1_HISTBIN@) +#define TA1_HISTCNT (@TA1_HISTCNT@) + +#endif /* defined(TA1_BASE) */ + +#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file diff --git a/source/hal/platform/simple/include/platform_drivers.h b/source/hal/platform/simple/include/platform_drivers.h new file mode 100644 index 0000000..0fb092e --- /dev/null +++ b/source/hal/platform/simple/include/platform_drivers.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_DRIVER_H +#define PLATFORM_DRIVER_H + +#include "log_macros.h" /* Logging related helpers. */ + +/* Platform components */ +#include "uart_stdout.h" /* stdout over UART. */ +#include "stubs/glcd.h" /* LCD stubs to support use cases that use LCD */ +#include "timer_simple_platform.h" /* timer implementation */ + +#include "cmsis.h" /* CPU device specific header file */ +#include "peripheral_memmap.h" /* peripheral memory map definitions */ +#include "peripheral_irqs.h" /* IRQ numbers for the platform */ + +#endif /* PLATFORM_DRIVER_H */ diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/include/stubs_simple_platform.h b/source/hal/platform/simple/include/stubs/glcd.h index 9977cd2..5915f7d 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/include/stubs_simple_platform.h +++ b/source/hal/platform/simple/include/stubs/glcd.h @@ -17,9 +17,6 @@ #ifndef STUBS_SIMPLE_PLATFORM_H #define STUBS_SIMPLE_PLATFORM_H -#include "cmsis.h" /* device specific header file */ -#include "peripheral_memmap.h" /* peripheral memory map definitions */ - /****************************************************************************/ /* Definitions and stub functions for modules currently */ /* unavailable on this target platform */ @@ -29,9 +26,6 @@ #define Black 0x0000 /* 0, 0, 0 */ #define White 0xFFFF /* 255, 255, 255 */ -/*********************** Clock related functions *****************************/ -uint32_t GetCoreClock(void); - /************************ GLCD related functions ****************************/ /** * @brief Initialize the Himax LCD with HX8347-D LCD Controller @@ -64,10 +58,10 @@ void GLCD_Bitmap(unsigned int x, unsigned int y, * @param[in] downsample_factor factor by which the image * is downsampled by. */ -void GLCD_Image(void *data, const uint32_t width, - const uint32_t height, const uint32_t channels, - const uint32_t pos_x, const uint32_t pos_y, - const uint32_t downsample_factor); +void GLCD_Image(void *data, const unsigned int width, + const unsigned int height, const unsigned int channels, + const unsigned int pos_x, const unsigned int pos_y, + const unsigned int downsample_factor); /** * @brief Clear display diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/include/timer_simple_platform.h b/source/hal/platform/simple/include/timer_simple_platform.h index 320a57a..03d8245 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/include/timer_simple_platform.h +++ b/source/hal/platform/simple/include/timer_simple_platform.h @@ -16,13 +16,12 @@ */ #ifndef TIMER_SIMPLE_PLATFORM_H #define TIMER_SIMPLE_PLATFORM_H - -#include "stubs_simple_platform.h" +#include <stdint.h> /* Container for timestamp for simple platform. */ typedef struct _generic_time_counter { uint64_t counter_systick; -} generic_time_counter; +} base_time_counter; /** * @brief Resets the counters. @@ -33,13 +32,13 @@ void timer_reset(void); * @brief Gets the current counter values. * @returns counter struct. **/ -generic_time_counter get_time_counter(void); +base_time_counter get_time_counter(void); /** * @brief Gets the cycle counts elapsed between start and end. * @return difference in counter values as 32 bit unsigned integer. */ -uint64_t get_cycle_count_diff(generic_time_counter *start, generic_time_counter *end); +uint64_t get_cycle_count_diff(base_time_counter *start, base_time_counter *end); /** * @brief Enables or triggers cycle counting mechanism, if required diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/stubs_simple_platform.c b/source/hal/platform/simple/source/stubs_glcd.c index df11adb..6b60dcd 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/stubs_simple_platform.c +++ b/source/hal/platform/simple/source/stubs_glcd.c @@ -14,17 +14,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include "stubs_simple_platform.h" - -#include "bsp_core_log.h" +#include "stubs/glcd.h" +#include "log_macros.h" #include <inttypes.h> -uint32_t GetCoreClock(void) -{ - return 1; -} - void GLCD_Initialize(void) {} void GLCD_Bitmap(unsigned int x, unsigned int y, @@ -37,9 +31,9 @@ void GLCD_Bitmap(unsigned int x, unsigned int y, UNUSED(bitmap); } -void GLCD_Image(void *data, const uint32_t width, const uint32_t height, - const uint32_t channels, const uint32_t pos_x, - const uint32_t pos_y, const uint32_t downsample_factor) +void GLCD_Image(void *data, const unsigned int width, const unsigned int height, + const unsigned int channels, const unsigned int pos_x, + const unsigned int pos_y, const unsigned int downsample_factor) { UNUSED(data); UNUSED(pos_x); @@ -93,22 +87,3 @@ void GLCD_Box(unsigned int x, unsigned int y, unsigned int w, unsigned int h, UNUSED(h); UNUSED(color); } - -void LED_Initialize(uint32_t port) -{ - UNUSED(port); -} - -void LED_On(uint32_t num, uint32_t port) -{ - UNUSED(num); - UNUSED(port); - debug("LED %" PRIu32 " ON\n", num); -} - -void LED_Off(uint32_t num, uint32_t port) -{ - UNUSED(num); - UNUSED(port); - debug("LED %" PRIu32 " OFF\n", num); -} diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/timer_simple_platform.c b/source/hal/platform/simple/source/timer_simple_platform.c index 6914209..4bcd07b 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/simple_platform/timer_simple_platform.c +++ b/source/hal/platform/simple/source/timer_simple_platform.c @@ -17,13 +17,13 @@ #include "timer_simple_platform.h" #include "irqs.h" -#include "bsp_core_log.h" +#include "log_macros.h" #include <inttypes.h> -generic_time_counter get_time_counter(void) +base_time_counter get_time_counter(void) { - generic_time_counter t = { + base_time_counter t = { .counter_systick = Get_SysTick_Cycle_Count() }; debug("counter_systick: %" PRIu64 "\n", t.counter_systick); @@ -38,8 +38,8 @@ void timer_reset(void) debug("system tick config ready\n"); } -uint64_t get_cycle_count_diff(generic_time_counter *start, - generic_time_counter *end) +uint64_t get_cycle_count_diff(base_time_counter *start, + base_time_counter *end) { if (start->counter_systick > end->counter_systick) { warn("start > end; counter might have overflown\n"); diff --git a/source/hal/profiles/bare-metal/bsp/include/bsp.h b/source/hal/profiles/bare-metal/bsp/include/bsp.h new file mode 100644 index 0000000..e6dd0b5 --- /dev/null +++ b/source/hal/profiles/bare-metal/bsp/include/bsp.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef BSP_H +#define BSP_H + +#include "platform_drivers.h" + +#if defined(ARM_NPU) +#include "ethosu_mem_config.h" +#endif /* defined(ARM_NPU) */ + +#endif /* BSP_H */ diff --git a/source/application/hal/platforms/bare-metal/bsp/include/ethosu_mem_config.h b/source/hal/profiles/bare-metal/bsp/include/ethosu_mem_config.h index b393a03..b393a03 100644 --- a/source/application/hal/platforms/bare-metal/bsp/include/ethosu_mem_config.h +++ b/source/hal/profiles/bare-metal/bsp/include/ethosu_mem_config.h diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-core/retarget.c b/source/hal/profiles/bare-metal/bsp/retarget.c index 29c2023..dfef62c 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-core/retarget.c +++ b/source/hal/profiles/bare-metal/bsp/retarget.c @@ -16,7 +16,6 @@ */ #include "uart_stdout.h" -#include "bsp_core_log.h" #include <stdio.h> #include <string.h> @@ -70,7 +69,7 @@ void _ttywrch(int ch) { FILEHANDLE RETARGET(_open)(const char *name, int openmode) { - UNUSED(openmode); + (void)(openmode); if (strcmp(name, __stdin_name) == 0) { return (STDIN); @@ -89,7 +88,7 @@ FILEHANDLE RETARGET(_open)(const char *name, int openmode) int RETARGET(_write)(FILEHANDLE fh, const unsigned char *buf, unsigned int len, int mode) { - UNUSED(mode); + (void)(mode); switch (fh) { case STDOUT: @@ -112,7 +111,7 @@ int RETARGET(_write)(FILEHANDLE fh, const unsigned char *buf, unsigned int len, int RETARGET(_read)(FILEHANDLE fh, unsigned char *buf, unsigned int len, int mode) { - UNUSED(mode); + (void)(mode); switch (fh) { case STDIN: { @@ -157,15 +156,15 @@ int RETARGET(_close)(FILEHANDLE fh) int RETARGET(_seek)(FILEHANDLE fh, long pos) { - UNUSED(fh); - UNUSED(pos); + (void)(fh); + (void)(pos); return -1; } int RETARGET(_ensure)(FILEHANDLE fh) { - UNUSED(fh); + (void)(fh); return -1; } @@ -181,16 +180,16 @@ long RETARGET(_flen)(FILEHANDLE fh) int RETARGET(_tmpnam)(char *name, int sig, unsigned int maxlen) { - UNUSED(name); - UNUSED(sig); - UNUSED(maxlen); + (void)(name); + (void)(sig); + (void)(maxlen); return 1; } char *RETARGET(_command_string)(char *cmd, int len) { - UNUSED(len); + (void)(len); return cmd; } @@ -198,11 +197,12 @@ char *RETARGET(_command_string)(char *cmd, int len) void RETARGET(_exit)(int return_code) { UartEndSimulation(return_code); + while(1); } int system(const char *cmd) { - UNUSED(cmd); + (void)(cmd); return 0; } @@ -228,29 +228,29 @@ clock_t clock(void) } int remove(const char *arg) { - UNUSED(arg); + (void)(arg); return 0; } int rename(const char *oldn, const char *newn) { - UNUSED(oldn); - UNUSED(newn); + (void)(oldn); + (void)(newn); return 0; } int fputc(int ch, FILE *f) { - UNUSED(f); + (void)(f); return UartPutc(ch); } int fgetc(FILE *f) { - UNUSED(f); + (void)(f); return UartPutc(UartGetc()); } @@ -260,7 +260,7 @@ int fgetc(FILE *f) /* arm-none-eabi-gcc with newlib uses a define for ferror */ int ferror(FILE *f) { - UNUSED(f); + (void)(f); return EOF; } diff --git a/source/application/hal/platforms/bare-metal/data_acquisition/data_acq.c b/source/hal/profiles/bare-metal/data_acquisition/data_acq.c index 1e40b02..1e40b02 100644 --- a/source/application/hal/platforms/bare-metal/data_acquisition/data_acq.c +++ b/source/hal/profiles/bare-metal/data_acquisition/data_acq.c diff --git a/source/application/hal/platforms/bare-metal/data_presentation/data_psn.c b/source/hal/profiles/bare-metal/data_presentation/data_psn.c index 474d552..474d552 100644 --- a/source/application/hal/platforms/bare-metal/data_presentation/data_psn.c +++ b/source/hal/profiles/bare-metal/data_presentation/data_psn.c diff --git a/source/application/hal/platforms/bare-metal/data_presentation/lcd/include/lcd_img.h b/source/hal/profiles/bare-metal/data_presentation/lcd/include/lcd_img.h index e4ad791..e4ad791 100644 --- a/source/application/hal/platforms/bare-metal/data_presentation/lcd/include/lcd_img.h +++ b/source/hal/profiles/bare-metal/data_presentation/lcd/include/lcd_img.h diff --git a/source/application/hal/platforms/bare-metal/data_presentation/lcd/lcd_img.c b/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c index f03566f..f03566f 100644 --- a/source/application/hal/platforms/bare-metal/data_presentation/lcd/lcd_img.c +++ b/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c diff --git a/source/application/hal/platforms/bare-metal/timer/include/baremetal_timer.h b/source/hal/profiles/bare-metal/timer/include/platform_timer.h index 0d23a05..6338e0b 100644 --- a/source/application/hal/platforms/bare-metal/timer/include/baremetal_timer.h +++ b/source/hal/profiles/bare-metal/timer/include/platform_timer.h @@ -17,17 +17,11 @@ #ifndef BAREMETAL_TIMER_H #define BAREMETAL_TIMER_H +#include "bsp.h" + #include <stdint.h> #include <time.h> -#if defined (MPS3_PLATFORM) - #include "timer_mps3.h" - typedef mps3_time_counter base_time_counter; -#else /* defined (MPS3_PLATFORM) */ - #include "timer_simple_platform.h" - typedef generic_time_counter base_time_counter; -#endif /* defined (MPS3_PLATFORM) */ - typedef struct bm_time_counter { base_time_counter counter; diff --git a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c b/source/hal/profiles/bare-metal/timer/platform_timer.c index c8e7252..c8e7252 100644 --- a/source/application/hal/platforms/bare-metal/timer/baremetal_timer.c +++ b/source/hal/profiles/bare-metal/timer/platform_timer.c diff --git a/source/application/hal/platforms/bare-metal/utils/include/system_init.h b/source/hal/profiles/bare-metal/utils/include/system_init.h index 84e0305..84e0305 100644 --- a/source/application/hal/platforms/bare-metal/utils/include/system_init.h +++ b/source/hal/profiles/bare-metal/utils/include/system_init.h diff --git a/source/application/hal/platforms/bare-metal/utils/system_init.c b/source/hal/profiles/bare-metal/utils/system_init.c index 376f08b..23af14f 100644 --- a/source/application/hal/platforms/bare-metal/utils/system_init.c +++ b/source/hal/profiles/bare-metal/utils/system_init.c @@ -16,8 +16,6 @@ */ #include "system_init.h" -#include "uart_stdout.h" - #include <string.h> #include <inttypes.h> diff --git a/source/application/hal/platforms/native/data_acquisition/data_acq.c b/source/hal/profiles/native/data_acquisition/data_acq.c index 9b6815b..9b6815b 100644 --- a/source/application/hal/platforms/native/data_acquisition/data_acq.c +++ b/source/hal/profiles/native/data_acquisition/data_acq.c diff --git a/source/application/hal/platforms/native/data_presentation/data_psn.c b/source/hal/profiles/native/data_presentation/data_psn.c index fe4bcfa..fe4bcfa 100644 --- a/source/application/hal/platforms/native/data_presentation/data_psn.c +++ b/source/hal/profiles/native/data_presentation/data_psn.c diff --git a/source/application/hal/platforms/native/data_presentation/log/include/log.h b/source/hal/profiles/native/data_presentation/log/include/log.h index 9b9928f..9b9928f 100644 --- a/source/application/hal/platforms/native/data_presentation/log/include/log.h +++ b/source/hal/profiles/native/data_presentation/log/include/log.h diff --git a/source/application/hal/platforms/native/data_presentation/log/log.c b/source/hal/profiles/native/data_presentation/log/log.c index 8dffba9..1673af1 100644 --- a/source/application/hal/platforms/native/data_presentation/log/log.c +++ b/source/hal/profiles/native/data_presentation/log/log.c @@ -15,8 +15,7 @@ * limitations under the License. */ #include "log.h" - -#include "dummy_log.h" +#include "log_macros.h" #include <stdint.h> diff --git a/source/application/hal/platforms/native/timer/include/native_timer.h b/source/hal/profiles/native/timer/include/platform_timer.h index df7b493..df7b493 100644 --- a/source/application/hal/platforms/native/timer/include/native_timer.h +++ b/source/hal/profiles/native/timer/include/platform_timer.h diff --git a/source/application/hal/platforms/native/timer/native_timer.cc b/source/hal/profiles/native/timer/platform_timer.c index c115f4d..c311125 100644 --- a/source/application/hal/platforms/native/timer/native_timer.cc +++ b/source/hal/profiles/native/timer/platform_timer.c @@ -20,9 +20,9 @@ extern "C" { #include "timer.h" -#include <cassert> -#include <ctime> -#include <cstring> +#include <assert.h> +#include <time.h> +#include <string.h> #define MILLISECONDS_IN_SECOND 1000 #define MICROSECONDS_IN_SECOND 1000000 @@ -35,7 +35,7 @@ extern "C" { **/ static time_counter get_time_counter(void) { - struct timespec current_time{}; + struct timespec current_time; clock_gettime(1, ¤t_time); time_counter t = { .current_secs = current_time.tv_sec, diff --git a/source/application/hal/platforms/native/utils/include/system_init.h b/source/hal/profiles/native/utils/include/system_init.h index 80b1bb2..5d3fcd0 100644 --- a/source/application/hal/platforms/native/utils/include/system_init.h +++ b/source/hal/profiles/native/utils/include/system_init.h @@ -17,8 +17,7 @@ #ifndef NATIVE_SYSTEM_INIT_H #define NATIVE_SYSTEM_INIT_H -#include "dummy_log.h" - +#include <stddef.h> /** * @brief Platform initialisation for native platform. **/ diff --git a/source/application/hal/platforms/native/utils/system_init.c b/source/hal/profiles/native/utils/system_init.c index 8e0b768..8e0b768 100644 --- a/source/application/hal/platforms/native/utils/system_init.c +++ b/source/hal/profiles/native/utils/system_init.c diff --git a/source/log/CMakeLists.txt b/source/log/CMakeLists.txt new file mode 100644 index 0000000..1de737e --- /dev/null +++ b/source/log/CMakeLists.txt @@ -0,0 +1,43 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +####################################################### +# Header-only logging definitions as an interface lib.# +####################################################### +cmake_minimum_required(VERSION 3.15.6) + +set(BSP_LOGGING_TARGET log) + +project(${BSP_LOGGING_TARGET} + DESCRIPTION "Generic logging formatting header-only interface lib." + LANGUAGES C) + +add_library(${BSP_LOGGING_TARGET} INTERFACE) + +if (DEFINED LOG_LEVEL) + message(STATUS "Setting log level to ${LOG_LEVEL}") + target_compile_definitions(${BSP_LOGGING_TARGET} + INTERFACE + LOG_LEVEL=${LOG_LEVEL}) +endif() + +target_include_directories(${BSP_LOGGING_TARGET} INTERFACE include) + +message(STATUS "*******************************************************") +message(STATUS "Library : " ${BSP_LOGGING_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-core/include/bsp_core_log.h b/source/log/include/log_macros.h index ffb55e7..15f4dd5 100644 --- a/source/application/hal/platforms/bare-metal/bsp/bsp-core/include/bsp_core_log.h +++ b/source/log/include/log_macros.h @@ -14,12 +14,15 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef BSP_CORE_LOG_H -#define BSP_CORE_LOG_H +#ifndef ML_EMBEDDED_CORE_LOG_H +#define ML_EMBEDDED_CORE_LOG_H -#include "uart_stdout.h" /* UART for logging */ +#ifdef __cplusplus +extern "C" { +#endif #include <stdio.h> +#include <inttypes.h> #define LOG_LEVEL_TRACE 0 #define LOG_LEVEL_DEBUG 1 @@ -31,6 +34,8 @@ #define LOG_LEVEL LOG_LEVEL_INFO #endif /*LOG_LEVEL*/ +#define UNUSED(x) ((void)(x)) + #if (LOG_LEVEL == LOG_LEVEL_TRACE) #define trace(...) printf("TRACE - "); printf(__VA_ARGS__) #else @@ -61,6 +66,8 @@ #define printf_err(...) #endif /* LOG_LEVEL > LOG_LEVEL_INFO */ -#define UNUSED(x) ((void)(x)) +#ifdef __cplusplus +} +#endif -#endif /* BSP_CORE_LOG_H */ +#endif /* ML_EMBEDDED_CORE_LOG_H */
\ No newline at end of file diff --git a/source/math/CMakeLists.txt b/source/math/CMakeLists.txt new file mode 100644 index 0000000..eab6622 --- /dev/null +++ b/source/math/CMakeLists.txt @@ -0,0 +1,44 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +####################################################### +# Math functions for ML pipelines. # +####################################################### + +project(arm_math + DESCRIPTION "Collection of the optimised math functions for ML pipelines" + LANGUAGES C CXX) + +add_library(arm_math STATIC) + +target_sources(arm_math + PRIVATE + PlatformMath.cc) + +target_include_directories(arm_math PUBLIC include) + +target_link_libraries(arm_math PRIVATE log) + +if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m55) + include(${CMAKE_SCRIPTS_DIR}/cmsis-dsp.cmake) + target_link_libraries(arm_math PUBLIC cmsis-dsp) +endif () + +message(STATUS "*******************************************************") +message(STATUS "Library : " arm_math) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/application/main/PlatformMath.cc b/source/math/PlatformMath.cc index 26b4b72..cc603f3 100644 --- a/source/application/main/PlatformMath.cc +++ b/source/math/PlatformMath.cc @@ -15,13 +15,8 @@ * limitations under the License. */ #include "PlatformMath.hpp" +#include "log_macros.h" #include <algorithm> -#include <numeric> - -#if 0 == ARM_DSP_AVAILABLE - #include <cmath> - #include <numeric> -#endif /* 0 == ARM_DSP_AVAILABLE */ namespace arm { namespace app { @@ -29,31 +24,31 @@ namespace math { float MathUtils::CosineF32(float radians) { -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP return arm_cos_f32(radians); -#else /* ARM_DSP_AVAILABLE */ - return cos(radians); -#endif /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ + return cosf(radians); +#endif /* ARM_MATH_DSP */ } float MathUtils::SineF32(float radians) { -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP return arm_sin_f32(radians); -#else /* ARM_DSP_AVAILABLE */ - return sin(radians); -#endif /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ + return sinf(radians); +#endif /* ARM_MATH_DSP */ } float MathUtils::SqrtF32(float input) { -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP float output = 0.f; arm_sqrt_f32(input, &output); return output; -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ return sqrtf(input); -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ } float MathUtils::MeanF32(float* ptrSrc, const uint32_t srcLen) @@ -62,14 +57,14 @@ namespace math { return 0.f; } -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP float result = 0.f; arm_mean_f32(ptrSrc, srcLen, &result); return result; -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ float acc = std::accumulate(ptrSrc, ptrSrc + srcLen, 0.0); return acc/srcLen; -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ } float MathUtils::StdDevF32(float* ptrSrc, const uint32_t srcLen, @@ -78,7 +73,7 @@ namespace math { if (!srcLen) { return 0.f; } -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP /** * Note Standard deviation calculation can be off * by > 0.01 but less than < 0.1, according to @@ -88,7 +83,7 @@ namespace math { float stdDev = 0; arm_std_f32(ptrSrc, srcLen, &stdDev); return stdDev; -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ auto VarianceFunction = [=](float acc, const float value) { return acc + (((value - mean) * (value - mean))/ srcLen); }; @@ -97,7 +92,7 @@ namespace math { VarianceFunction); return sqrtf(acc); -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ } void MathUtils::FftInitF32(const uint16_t fftLen, @@ -109,7 +104,7 @@ namespace math { fftInstance.m_optimisedOptionAvailable = false; fftInstance.m_type = type; -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP arm_status status = ARM_MATH_ARGUMENT_ERROR; switch (fftInstance.m_type) { case FftType::real: @@ -130,11 +125,9 @@ namespace math { } else { fftInstance.m_optimisedOptionAvailable = true; } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ - if (!fftInstance.m_optimisedOptionAvailable) { - debug("Non optimised FFT will be used\n."); - } + debug("Optimised FFT will be used: %s.\n", fftInstance.m_optimisedOptionAvailable? "yes": "no"); fftInstance.m_initialised = true; } @@ -157,7 +150,7 @@ namespace math { float sumReal = 0; float sumImag = 0; - const float theta = static_cast<float>(2 * M_PI * k / inputLength); + const auto theta = static_cast<float>(2 * M_PI * k / inputLength); for (size_t t = 0; t < inputLength; t++) { const auto angle = static_cast<float>(t * theta); @@ -210,12 +203,12 @@ namespace math { switch (fftInstance.m_type) { case FftType::real: -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP if (fftInstance.m_optimisedOptionAvailable) { arm_rfft_fast_f32(&fftInstance.m_instanceReal, input.data(), fftOutput.data(), 0); return; } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ FftRealF32(input, fftOutput); return; @@ -224,13 +217,13 @@ namespace math { printf_err("Complex FFT instance should have input size >= (FFT len x 2)"); return; } -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP if (fftInstance.m_optimisedOptionAvailable) { fftOutput = input; /* Complex function works in-place */ arm_cfft_f32(&fftInstance.m_instanceComplex, fftOutput.data(), 0, 1); return; } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ FftComplexF32(input, fftOutput); return; @@ -243,15 +236,15 @@ namespace math { void MathUtils::VecLogarithmF32(std::vector <float>& input, std::vector <float>& output) { -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP arm_vlog_f32(input.data(), output.data(), output.size()); -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ for (auto in = input.begin(), out = output.begin(); in != input.end() && out != output.end(); ++in, ++out) { *out = logf(*in); } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ } float MathUtils::DotProductF32(float* srcPtrA, float* srcPtrB, @@ -259,13 +252,13 @@ namespace math { { float output = 0.f; -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP arm_dot_prod_f32(srcPtrA, srcPtrB, srcLen, &output); -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ for (uint32_t i = 0; i < srcLen; ++i) { output += *srcPtrA++ * *srcPtrB++; } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ return output; } @@ -280,15 +273,15 @@ namespace math { return false; } -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP arm_cmplx_mag_squared_f32(ptrSrc, ptrDst, srcLen/2); -#else /* ARM_DSP_AVAILABLE */ +#else /* ARM_MATH_DSP */ for (uint32_t j = 0; j < srcLen/2; ++j) { const float real = *ptrSrc++; const float im = *ptrSrc++; *ptrDst++ = real*real + im*im; } -#endif /* ARM_DSP_AVAILABLE */ +#endif /* ARM_MATH_DSP */ return true; } diff --git a/source/application/main/include/PlatformMath.hpp b/source/math/include/PlatformMath.hpp index fdb51b2..5ac10de 100644 --- a/source/application/main/include/PlatformMath.hpp +++ b/source/math/include/PlatformMath.hpp @@ -17,20 +17,18 @@ #ifndef PLATFORM_MATH_HPP #define PLATFORM_MATH_HPP -#include "hal.h" - /* See if ARM DSP functions can be used. */ -#if PLATFORM_HAL == PLATFORM_CORTEX_M_BAREMETAL - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - - #define ARM_DSP_AVAILABLE (1U) - #include "arm_math.h" - #define M_PI (PI) +#if defined(ARM_MATH_DSP) - #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) */ -#endif /* PLATFORM_HAL == PLATFORM_CORTEX_M_BAREMETAL */ + #include "arm_math.h" + #define M_PI (PI) +#else + #include <cmath> +#endif #include <vector> +#include <cstdint> +#include <numeric> namespace arm { namespace app { @@ -42,12 +40,12 @@ namespace math { }; struct FftInstance { -#if ARM_DSP_AVAILABLE +#if ARM_MATH_DSP arm_rfft_fast_instance_f32 m_instanceReal; arm_cfft_instance_f32 m_instanceComplex; #endif uint16_t m_fftLen{0}; - FftType m_type; + FftType m_type{FftType::real}; bool m_optimisedOptionAvailable{false}; bool m_initialised{false}; }; @@ -108,9 +106,9 @@ namespace math { * @param[in] fftInstance FFT instance struct to use. * @param[in] type FFT type (real or complex) */ - static void FftInitF32(const uint16_t fftLen, + static void FftInitF32(uint16_t fftLen, FftInstance& fftInstance, - const FftType type = FftType::real); + FftType type = FftType::real); /** * @brief Computes the FFT for the input vector. @@ -144,7 +142,7 @@ namespace math { * @return Dot product. */ static float DotProductF32(float* srcPtrA, float* srcPtrB, - const uint32_t srcLen); + uint32_t srcLen); /** * @brief Computes the squared magnitude of floating point @@ -157,9 +155,9 @@ namespace math { * @return true if successful, false otherwise. */ static bool ComplexMagnitudeSquaredF32(float* ptrSrc, - const uint32_t srcLen, + uint32_t srcLen, float* ptrDst, - const uint32_t dstLen); + uint32_t dstLen); /** * @brief Scales output scores for an arbitrary number of classes so diff --git a/source/use_case/ad/src/AdMelSpectrogram.cc b/source/use_case/ad/src/AdMelSpectrogram.cc index e070eb8..14b9323 100644 --- a/source/use_case/ad/src/AdMelSpectrogram.cc +++ b/source/use_case/ad/src/AdMelSpectrogram.cc @@ -15,8 +15,8 @@ * limitations under the License. */ #include "AdMelSpectrogram.hpp" - #include "PlatformMath.hpp" +#include "log_macros.h" #include <cfloat> diff --git a/source/use_case/ad/src/AdModel.cc b/source/use_case/ad/src/AdModel.cc index 82ad822..a2ef260 100644 --- a/source/use_case/ad/src/AdModel.cc +++ b/source/use_case/ad/src/AdModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "AdModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::AdModel::GetOpResolver() { diff --git a/source/use_case/ad/src/AdPostProcessing.cc b/source/use_case/ad/src/AdPostProcessing.cc index 157784b..c461875 100644 --- a/source/use_case/ad/src/AdPostProcessing.cc +++ b/source/use_case/ad/src/AdPostProcessing.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "AdPostProcessing.hpp" - -#include "hal.h" +#include "log_macros.h" #include <numeric> #include <cmath> diff --git a/source/use_case/ad/src/MainLoop.cc b/source/use_case/ad/src/MainLoop.cc index a323610..5a289bf 100644 --- a/source/use_case/ad/src/MainLoop.cc +++ b/source/use_case/ad/src/MainLoop.cc @@ -19,6 +19,7 @@ #include "AdModel.hpp" /* Model class for running inference */ #include "UseCaseCommonUtils.hpp" /* Utils functions */ #include "UseCaseHandler.hpp" /* Handlers for different user options */ +#include "log_macros.h" enum opcodes { diff --git a/source/use_case/ad/src/MelSpectrogram.cc b/source/use_case/ad/src/MelSpectrogram.cc index fa7714a..ff0c536 100644 --- a/source/use_case/ad/src/MelSpectrogram.cc +++ b/source/use_case/ad/src/MelSpectrogram.cc @@ -17,9 +17,10 @@ #include "MelSpectrogram.hpp" #include "PlatformMath.hpp" +#include "log_macros.h" #include <cfloat> -#include <inttypes.h> +#include <cinttypes> namespace arm { namespace app { diff --git a/source/use_case/ad/src/UseCaseHandler.cc b/source/use_case/ad/src/UseCaseHandler.cc index bc6ec7a..420e6d4 100644 --- a/source/use_case/ad/src/UseCaseHandler.cc +++ b/source/use_case/ad/src/UseCaseHandler.cc @@ -24,6 +24,7 @@ #include "AudioUtils.hpp" #include "UseCaseCommonUtils.hpp" #include "AdPostProcessing.hpp" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/asr/include/Wav2LetterPostprocess.hpp b/source/use_case/asr/include/Wav2LetterPostprocess.hpp index a744e0f..29eb548 100644 --- a/source/use_case/asr/include/Wav2LetterPostprocess.hpp +++ b/source/use_case/asr/include/Wav2LetterPostprocess.hpp @@ -18,7 +18,7 @@ #define ASR_WAV2LETTER_POSTPROCESS_HPP #include "TensorFlowLiteMicro.hpp" /* TensorFlow headers. */ -#include "hal.h" /* stdout facility. */ +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/asr/include/Wav2LetterPreprocess.hpp b/source/use_case/asr/include/Wav2LetterPreprocess.hpp index b0e0c67..13d1589 100644 --- a/source/use_case/asr/include/Wav2LetterPreprocess.hpp +++ b/source/use_case/asr/include/Wav2LetterPreprocess.hpp @@ -21,6 +21,7 @@ #include "Wav2LetterMfcc.hpp" #include "AudioUtils.hpp" #include "DataStructures.hpp" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/asr/src/AsrClassifier.cc b/source/use_case/asr/src/AsrClassifier.cc index a715068..84e66b7 100644 --- a/source/use_case/asr/src/AsrClassifier.cc +++ b/source/use_case/asr/src/AsrClassifier.cc @@ -16,7 +16,7 @@ */ #include "AsrClassifier.hpp" -#include "hal.h" +#include "log_macros.h" #include "TensorFlowLiteMicro.hpp" #include "Wav2LetterModel.hpp" diff --git a/source/use_case/asr/src/MainLoop.cc b/source/use_case/asr/src/MainLoop.cc index 87145f4..40624f3 100644 --- a/source/use_case/asr/src/MainLoop.cc +++ b/source/use_case/asr/src/MainLoop.cc @@ -23,6 +23,7 @@ #include "InputFiles.hpp" /* Generated audio clip header. */ #include "Wav2LetterPreprocess.hpp" /* Pre-processing class. */ #include "Wav2LetterPostprocess.hpp" /* Post-processing class. */ +#include "log_macros.h" enum opcodes { diff --git a/source/use_case/asr/src/UseCaseHandler.cc b/source/use_case/asr/src/UseCaseHandler.cc index f13de0d..afcb6e4 100644 --- a/source/use_case/asr/src/UseCaseHandler.cc +++ b/source/use_case/asr/src/UseCaseHandler.cc @@ -27,6 +27,7 @@ #include "Wav2LetterPreprocess.hpp" #include "Wav2LetterPostprocess.hpp" #include "OutputDecode.hpp" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/asr/src/Wav2LetterMfcc.cc b/source/use_case/asr/src/Wav2LetterMfcc.cc index 0eb152a..1bcaa66 100644 --- a/source/use_case/asr/src/Wav2LetterMfcc.cc +++ b/source/use_case/asr/src/Wav2LetterMfcc.cc @@ -15,8 +15,8 @@ * limitations under the License. */ #include "Wav2LetterMfcc.hpp" - #include "PlatformMath.hpp" +#include "log_macros.h" #include <cfloat> diff --git a/source/use_case/asr/src/Wav2LetterModel.cc b/source/use_case/asr/src/Wav2LetterModel.cc index a22dc55..766bce9 100644 --- a/source/use_case/asr/src/Wav2LetterModel.cc +++ b/source/use_case/asr/src/Wav2LetterModel.cc @@ -15,8 +15,8 @@ * limitations under the License. */ #include "Wav2LetterModel.hpp" +#include "log_macros.h" -#include "hal.h" const tflite::MicroOpResolver& arm::app::Wav2LetterModel::GetOpResolver() { diff --git a/source/use_case/asr/src/Wav2LetterPostprocess.cc b/source/use_case/asr/src/Wav2LetterPostprocess.cc index fd11eef..0392061 100644 --- a/source/use_case/asr/src/Wav2LetterPostprocess.cc +++ b/source/use_case/asr/src/Wav2LetterPostprocess.cc @@ -15,9 +15,8 @@ * limitations under the License. */ #include "Wav2LetterPostprocess.hpp" - #include "Wav2LetterModel.hpp" - +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/img_class/src/MainLoop.cc b/source/use_case/img_class/src/MainLoop.cc index cab360b..05322d1 100644 --- a/source/use_case/img_class/src/MainLoop.cc +++ b/source/use_case/img_class/src/MainLoop.cc @@ -21,6 +21,7 @@ #include "MobileNetModel.hpp" /* Model class for running inference. */ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "UseCaseCommonUtils.hpp" /* Utils functions. */ +#include "log_macros.h" using ImgClassClassifier = arm::app::Classifier; diff --git a/source/use_case/img_class/src/MobileNetModel.cc b/source/use_case/img_class/src/MobileNetModel.cc index b937382..2e48f3b 100644 --- a/source/use_case/img_class/src/MobileNetModel.cc +++ b/source/use_case/img_class/src/MobileNetModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "MobileNetModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::MobileNetModel::GetOpResolver() { diff --git a/source/use_case/img_class/src/UseCaseHandler.cc b/source/use_case/img_class/src/UseCaseHandler.cc index 3812d81..fafc6b9 100644 --- a/source/use_case/img_class/src/UseCaseHandler.cc +++ b/source/use_case/img_class/src/UseCaseHandler.cc @@ -21,8 +21,9 @@ #include "MobileNetModel.hpp" #include "UseCaseCommonUtils.hpp" #include "hal.h" +#include "log_macros.h" -#include <inttypes.h> +#include <cinttypes> using ImgClassClassifier = arm::app::Classifier; @@ -108,7 +109,7 @@ namespace app { /* Display message on the LCD - inference running. */ platform.data_psn->present_data_text(str_inf.c_str(), str_inf.size(), - dataPsnTxtInfStartX, dataPsnTxtInfStartY, 0); + dataPsnTxtInfStartX, dataPsnTxtInfStartY, false); /* Run inference over this image. */ info("Running inference on image %" PRIu32 " => %s\n", ctx.Get<uint32_t>("imgIndex"), @@ -121,12 +122,12 @@ namespace app { /* Erase. */ str_inf = std::string(str_inf.size(), ' '); platform.data_psn->present_data_text(str_inf.c_str(), str_inf.size(), - dataPsnTxtInfStartX, dataPsnTxtInfStartY, 0); + dataPsnTxtInfStartX, dataPsnTxtInfStartY, false); auto& classifier = ctx.Get<ImgClassClassifier&>("classifier"); classifier.GetClassificationResults(outputTensor, results, ctx.Get<std::vector <std::string>&>("labels"), - 5); + 5, false); /* Add results to context for access outside handler. */ ctx.Set<std::vector<ClassificationResult>>("results", results); diff --git a/source/use_case/inference_runner/src/MainLoop.cc b/source/use_case/inference_runner/src/MainLoop.cc index 26a20de..cfdc520 100644 --- a/source/use_case/inference_runner/src/MainLoop.cc +++ b/source/use_case/inference_runner/src/MainLoop.cc @@ -18,6 +18,7 @@ #include "TestModel.hpp" /* Model class for running inference. */ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "UseCaseCommonUtils.hpp" /* Utils functions. */ +#include "log_macros.h" enum opcodes { diff --git a/source/use_case/inference_runner/src/TestModel.cc b/source/use_case/inference_runner/src/TestModel.cc index 274790f..3e72119 100644 --- a/source/use_case/inference_runner/src/TestModel.cc +++ b/source/use_case/inference_runner/src/TestModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "TestModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::AllOpsResolver& arm::app::TestModel::GetOpResolver() { diff --git a/source/use_case/inference_runner/src/UseCaseHandler.cc b/source/use_case/inference_runner/src/UseCaseHandler.cc index 78d99b0..1125830 100644 --- a/source/use_case/inference_runner/src/UseCaseHandler.cc +++ b/source/use_case/inference_runner/src/UseCaseHandler.cc @@ -19,6 +19,7 @@ #include "TestModel.hpp" #include "UseCaseCommonUtils.hpp" #include "hal.h" +#include "log_macros.h" #include <cstdlib> diff --git a/source/use_case/kws/src/MainLoop.cc b/source/use_case/kws/src/MainLoop.cc index bde246b..044c957 100644 --- a/source/use_case/kws/src/MainLoop.cc +++ b/source/use_case/kws/src/MainLoop.cc @@ -21,6 +21,7 @@ #include "Labels.hpp" /* For label strings. */ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "UseCaseCommonUtils.hpp" /* Utils functions. */ +#include "log_macros.h" using KwsClassifier = arm::app::Classifier; diff --git a/source/use_case/kws/src/MicroNetKwsModel.cc b/source/use_case/kws/src/MicroNetKwsModel.cc index 48a9b8c..1c38525 100644 --- a/source/use_case/kws/src/MicroNetKwsModel.cc +++ b/source/use_case/kws/src/MicroNetKwsModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "MicroNetKwsModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::MicroNetKwsModel::GetOpResolver() { diff --git a/source/use_case/kws/src/UseCaseHandler.cc b/source/use_case/kws/src/UseCaseHandler.cc index 8085af7..c2d2ea4 100644 --- a/source/use_case/kws/src/UseCaseHandler.cc +++ b/source/use_case/kws/src/UseCaseHandler.cc @@ -24,6 +24,7 @@ #include "AudioUtils.hpp" #include "UseCaseCommonUtils.hpp" #include "KwsResult.hpp" +#include "log_macros.h" #include <vector> #include <functional> diff --git a/source/use_case/kws_asr/include/Wav2LetterPostprocess.hpp b/source/use_case/kws_asr/include/Wav2LetterPostprocess.hpp index 5c11412..029a641 100644 --- a/source/use_case/kws_asr/include/Wav2LetterPostprocess.hpp +++ b/source/use_case/kws_asr/include/Wav2LetterPostprocess.hpp @@ -18,7 +18,6 @@ #define KWS_ASR_WAV2LET_POSTPROC_HPP #include "TensorFlowLiteMicro.hpp" /* TensorFlow headers */ -#include "hal.h" /* stdout facility */ namespace arm { namespace app { diff --git a/source/use_case/kws_asr/include/Wav2LetterPreprocess.hpp b/source/use_case/kws_asr/include/Wav2LetterPreprocess.hpp index 66d19d3..3609c49 100644 --- a/source/use_case/kws_asr/include/Wav2LetterPreprocess.hpp +++ b/source/use_case/kws_asr/include/Wav2LetterPreprocess.hpp @@ -21,6 +21,7 @@ #include "Wav2LetterMfcc.hpp" #include "AudioUtils.hpp" #include "DataStructures.hpp" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/kws_asr/src/AsrClassifier.cc b/source/use_case/kws_asr/src/AsrClassifier.cc index 3f9cd7b..9c18b14 100644 --- a/source/use_case/kws_asr/src/AsrClassifier.cc +++ b/source/use_case/kws_asr/src/AsrClassifier.cc @@ -16,7 +16,7 @@ */ #include "AsrClassifier.hpp" -#include "hal.h" +#include "log_macros.h" #include "TensorFlowLiteMicro.hpp" #include "Wav2LetterModel.hpp" diff --git a/source/use_case/kws_asr/src/MainLoop.cc b/source/use_case/kws_asr/src/MainLoop.cc index c7e977f..a2beab3 100644 --- a/source/use_case/kws_asr/src/MainLoop.cc +++ b/source/use_case/kws_asr/src/MainLoop.cc @@ -26,6 +26,7 @@ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "Wav2LetterPreprocess.hpp" /* ASR pre-processing class. */ #include "Wav2LetterPostprocess.hpp"/* ASR post-processing class. */ +#include "log_macros.h" using KwsClassifier = arm::app::Classifier; diff --git a/source/use_case/kws_asr/src/MicroNetKwsModel.cc b/source/use_case/kws_asr/src/MicroNetKwsModel.cc index 4b44580..663faa0 100644 --- a/source/use_case/kws_asr/src/MicroNetKwsModel.cc +++ b/source/use_case/kws_asr/src/MicroNetKwsModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "MicroNetKwsModel.hpp" - -#include "hal.h" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/kws_asr/src/UseCaseHandler.cc b/source/use_case/kws_asr/src/UseCaseHandler.cc index a3ebdb1..bfc1d25 100644 --- a/source/use_case/kws_asr/src/UseCaseHandler.cc +++ b/source/use_case/kws_asr/src/UseCaseHandler.cc @@ -30,6 +30,7 @@ #include "AsrResult.hpp" #include "AsrClassifier.hpp" #include "OutputDecode.hpp" +#include "log_macros.h" using KwsClassifier = arm::app::Classifier; diff --git a/source/use_case/kws_asr/src/Wav2LetterMfcc.cc b/source/use_case/kws_asr/src/Wav2LetterMfcc.cc index ae9e57a..f2c50f3 100644 --- a/source/use_case/kws_asr/src/Wav2LetterMfcc.cc +++ b/source/use_case/kws_asr/src/Wav2LetterMfcc.cc @@ -17,6 +17,7 @@ #include "Wav2LetterMfcc.hpp" #include "PlatformMath.hpp" +#include "log_macros.h" #include <cfloat> diff --git a/source/use_case/kws_asr/src/Wav2LetterModel.cc b/source/use_case/kws_asr/src/Wav2LetterModel.cc index affa1a6..52bd23a 100644 --- a/source/use_case/kws_asr/src/Wav2LetterModel.cc +++ b/source/use_case/kws_asr/src/Wav2LetterModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "Wav2LetterModel.hpp" - -#include "hal.h" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/kws_asr/src/Wav2LetterPostprocess.cc b/source/use_case/kws_asr/src/Wav2LetterPostprocess.cc index f2d9357..2a76b1b 100644 --- a/source/use_case/kws_asr/src/Wav2LetterPostprocess.cc +++ b/source/use_case/kws_asr/src/Wav2LetterPostprocess.cc @@ -15,8 +15,8 @@ * limitations under the License. */ #include "Wav2LetterPostprocess.hpp" - #include "Wav2LetterModel.hpp" +#include "log_macros.h" namespace arm { namespace app { diff --git a/source/use_case/noise_reduction/src/MainLoop.cc b/source/use_case/noise_reduction/src/MainLoop.cc index 7d814a8..c6214e3 100644 --- a/source/use_case/noise_reduction/src/MainLoop.cc +++ b/source/use_case/noise_reduction/src/MainLoop.cc @@ -20,6 +20,7 @@ #include "RNNoiseModel.hpp" /* Model class for running inference. */ #include "InputFiles.hpp" /* For input audio clips. */ #include "RNNoiseProcess.hpp" /* Pre-processing class */ +#include "log_macros.h" enum opcodes { diff --git a/source/use_case/noise_reduction/src/RNNoiseModel.cc b/source/use_case/noise_reduction/src/RNNoiseModel.cc index be0f369..244fa1a 100644 --- a/source/use_case/noise_reduction/src/RNNoiseModel.cc +++ b/source/use_case/noise_reduction/src/RNNoiseModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "RNNoiseModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::RNNoiseModel::GetOpResolver() { diff --git a/source/use_case/noise_reduction/src/RNNoiseProcess.cc b/source/use_case/noise_reduction/src/RNNoiseProcess.cc index d5b577e..4c568fa 100644 --- a/source/use_case/noise_reduction/src/RNNoiseProcess.cc +++ b/source/use_case/noise_reduction/src/RNNoiseProcess.cc @@ -15,6 +15,8 @@ * limitations under the License. */ #include "RNNoiseProcess.hpp" +#include "log_macros.h" + #include <algorithm> #include <cmath> #include <cstring> diff --git a/source/use_case/noise_reduction/src/UseCaseHandler.cc b/source/use_case/noise_reduction/src/UseCaseHandler.cc index 12b4ab3..0c5984c 100644 --- a/source/use_case/noise_reduction/src/UseCaseHandler.cc +++ b/source/use_case/noise_reduction/src/UseCaseHandler.cc @@ -14,16 +14,17 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include <cmath> -#include <algorithm> - -#include "UseCaseHandler.hpp" #include "hal.h" +#include "UseCaseHandler.hpp" #include "UseCaseCommonUtils.hpp" #include "AudioUtils.hpp" #include "InputFiles.hpp" #include "RNNoiseModel.hpp" #include "RNNoiseProcess.hpp" +#include "log_macros.h" + +#include <cmath> +#include <algorithm> namespace arm { namespace app { diff --git a/source/use_case/object_detection/src/MainLoop.cc b/source/use_case/object_detection/src/MainLoop.cc index d8fc7f5..4bec357 100644 --- a/source/use_case/object_detection/src/MainLoop.cc +++ b/source/use_case/object_detection/src/MainLoop.cc @@ -20,7 +20,7 @@ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "UseCaseCommonUtils.hpp" /* Utils functions. */ #include "DetectorPostProcessing.hpp" /* Post-processing class. */ - +#include "log_macros.h" static void DisplayDetectionMenu() { diff --git a/source/use_case/object_detection/src/UseCaseHandler.cc b/source/use_case/object_detection/src/UseCaseHandler.cc index ce3ef06..620ce6c 100644 --- a/source/use_case/object_detection/src/UseCaseHandler.cc +++ b/source/use_case/object_detection/src/UseCaseHandler.cc @@ -20,8 +20,9 @@ #include "UseCaseCommonUtils.hpp" #include "DetectorPostProcessing.hpp" #include "hal.h" +#include "log_macros.h" -#include <inttypes.h> +#include <cinttypes> namespace arm { namespace app { @@ -151,7 +152,8 @@ namespace app { dataPsnImgStartX, dataPsnImgStartY, dataPsnImgDownscaleFactor); #if VERIFY_TEST_OUTPUT - arm::app::DumpTensor(outputTensor); + arm::app::DumpTensor(modelOutput0); + arm::app::DumpTensor(modelOutput1); #endif /* VERIFY_TEST_OUTPUT */ if (!PresentInferenceResult(platform, results)) { diff --git a/source/use_case/object_detection/src/YoloFastestModel.cc b/source/use_case/object_detection/src/YoloFastestModel.cc index a8afd59..b1fd776 100644 --- a/source/use_case/object_detection/src/YoloFastestModel.cc +++ b/source/use_case/object_detection/src/YoloFastestModel.cc @@ -16,7 +16,7 @@ */ #include "YoloFastestModel.hpp" -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::YoloFastestModel::GetOpResolver() { diff --git a/source/use_case/vww/src/MainLoop.cc b/source/use_case/vww/src/MainLoop.cc index b29238c..30e85bf 100644 --- a/source/use_case/vww/src/MainLoop.cc +++ b/source/use_case/vww/src/MainLoop.cc @@ -21,6 +21,7 @@ #include "VisualWakeWordModel.hpp" /* Model class for running inference. */ #include "UseCaseHandler.hpp" /* Handlers for different user options. */ #include "UseCaseCommonUtils.hpp" /* Utils functions. */ +#include "log_macros.h" using ViusalWakeWordClassifier = arm::app::Classifier; diff --git a/source/use_case/vww/src/UseCaseHandler.cc b/source/use_case/vww/src/UseCaseHandler.cc index e4dc479..01011e2 100644 --- a/source/use_case/vww/src/UseCaseHandler.cc +++ b/source/use_case/vww/src/UseCaseHandler.cc @@ -20,6 +20,7 @@ #include "InputFiles.hpp" #include "UseCaseCommonUtils.hpp" #include "hal.h" +#include "log_macros.h" #include <algorithm> @@ -133,7 +134,8 @@ namespace app { auto& classifier = ctx.Get<Classifier&>("classifier"); classifier.GetClassificationResults(outputTensor, results, - ctx.Get<std::vector <std::string>&>("labels"), 1); + ctx.Get<std::vector <std::string>&>("labels"), 1, + false); /* Add results to context for access outside handler. */ ctx.Set<std::vector<ClassificationResult>>("results", results); diff --git a/source/use_case/vww/src/VisualWakeWordModel.cc b/source/use_case/vww/src/VisualWakeWordModel.cc index 3067c7a..59beccc 100644 --- a/source/use_case/vww/src/VisualWakeWordModel.cc +++ b/source/use_case/vww/src/VisualWakeWordModel.cc @@ -15,8 +15,7 @@ * limitations under the License. */ #include "VisualWakeWordModel.hpp" - -#include "hal.h" +#include "log_macros.h" const tflite::MicroOpResolver& arm::app::VisualWakeWordModel::GetOpResolver() { |