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authorKshitij Sisodia <kshitij.sisodia@arm.com>2021-11-24 10:39:52 +0000
committerKshitij Sisodia <kshitij.sisodia@arm.com>2021-11-25 10:05:25 +0000
commit661959c6d2fabada5d465e9de8f84128e3f7b684 (patch)
tree3321ebb442c7ec1f7af454dd25d6bd1b54663587 /set_up_default_resources.py
parentb59ba684aef4bef16262a1825e787a55fc992f0d (diff)
downloadml-embedded-evaluation-kit-661959c6d2fabada5d465e9de8f84128e3f7b684.tar.gz
MLECO-2426: Support for new Corstone-300 app note AN552 rev B.
These changes will limit the use of FPGA internal SRAM from a max of 4MiB to 2MiB and the BRAM from 2MiB to 1MiB. Change-Id: I69c8e695aee26ff4f235bfe83ffd26efbd66f547
Diffstat (limited to 'set_up_default_resources.py')
-rwxr-xr-xset_up_default_resources.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/set_up_default_resources.py b/set_up_default_resources.py
index 3eff6bf..f364795 100755
--- a/set_up_default_resources.py
+++ b/set_up_default_resources.py
@@ -134,8 +134,8 @@ NPUConfig = namedtuple('NPUConfig',['config_name',
'ethos_u_npu_id',
'ethos_u_config_id'])
-# The default internal SRAM size for Corstone-300 implementation on MPS3
-mps3_max_sram_sz = 4 * 1024 * 1024 # 4 MiB
+# The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552
+mps3_max_sram_sz = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each)
def call_command(command: str) -> str: