MLECO-4825: Adding Arm Corstone-315 support

This patch adds initial support for MPS4 based Arm Corstone-315 FVPs.
The applications will execute on the FVP but with INITSVTOR set to
`0x12000000` explicitly. The default value is the 64kiB code region
at `0x11000000`. The linker scripts will be changed for the initial
boot logic and vector table to be moved to the code region.

This patch adds `source/hal/source/platform/mps4` directory. There is
considerable overlap with MPS3 platform and this is expected to be the
case until the support for MPS4 matures. Refactoring to pull in
common bits from these targets will follow. Same goes for the CMake
build support added under `scripts/cmake/platforms/mps4`.

Change-Id: I981be9e1ec57cfedcf7d340b4f19e5eb40b5cbd3
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Tested-by: mlecosys <mlecosys@arm.com>
Reviewed-by: Conor Kennedy <conor.kennedy@arm.com>
Reviewed-by: Alex Tawse <alex.tawse@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>

4 files changed, 489 insertions, 2 deletions

diff --git a/scripts/cmake/platforms/mps4/build_configuration.cmake b/scripts/cmake/platforms/mps4/build_configuration.cmake
new file mode 100644
index 0000000..3a3966d
--- /dev/null
+++ b/scripts/cmake/platforms/mps4/build_configuration.cmake
@@ -0,0 +1,111 @@
+#----------------------------------------------------------------------------
+#  SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+function(set_platform_global_defaults)
+    message(STATUS "Platform: Arm MPS4 FPGA Prototyping Board or FVP")
+
+    if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
+        if(TARGET_SUBSYSTEM STREQUAL sse-315)
+            set(CMAKE_SYSTEM_PROCESSOR cortex-m85 CACHE STRING "Cortex-M CPU to use")
+        else()
+            message(FATAL_ERROR "${TARGET_SUBSYSTEM} unsupported by ${TARGET_PLATFORM}")
+        endif()
+    endif()
+
+    if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+        set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake
+                CACHE FILEPATH "Toolchain file")
+    endif()
+
+    # Arm Corstone-315's timing adapter behaviour is very different to Arm Corstone-300 and cannot
+    # be used for bandwidth/latency related performance sweeps for the Arm Ethos-U NPU. Read
+    # docs/sections/timing_adapters.md for more details.
+    if ((TARGET_SUBSYSTEM STREQUAL "sse-315") AND (DEFINED ETHOS_U_NPU_TIMING_ADAPTER_ENABLED))
+        message(STATUS "Timing adapter will NOT be used for target subsystem ${TARGET_SUBSYSTEM}")
+        set(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED OFF CACHE BOOL "Use of TA" FORCE)
+    endif()
+
+    set(LINKER_SCRIPT_NAME "mps4-${TARGET_SUBSYSTEM}" PARENT_SCOPE)
+    set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/mps4" PARENT_SCOPE)
+
+endfunction()
+
+function(platform_custom_post_build)
+    set(oneValueArgs TARGET_NAME)
+    cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} )
+
+    set_target_properties(${PARSED_TARGET_NAME} PROPERTIES SUFFIX ".axf")
+
+    # Add link options for the linker script to be used:
+    add_linker_script(
+            ${PARSED_TARGET_NAME}          # Target
+            ${CMAKE_SCRIPTS_DIR}/platforms/mps4/${TARGET_SUBSYSTEM}    # Directory path
+            ${LINKER_SCRIPT_NAME})  # Name of the file without suffix
+
+    add_target_map_file(
+            ${PARSED_TARGET_NAME}
+            ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.map)
+
+    set(SECTORS_DIR ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/sectors)
+    set(SECTORS_BIN_DIR ${SECTORS_DIR}/${use_case})
+
+    file(REMOVE_RECURSE ${SECTORS_BIN_DIR})
+    file(MAKE_DIRECTORY ${SECTORS_BIN_DIR})
+
+    if (TARGET_SUBSYSTEM STREQUAL sse-315)
+        set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
+        set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
+    endif()
+
+    add_bin_generation_command(
+            TARGET_NAME ${PARSED_TARGET_NAME}
+            OUTPUT_DIR  ${SECTORS_BIN_DIR}
+            AXF_PATH    ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf
+            SECTION_PATTERNS    "${LINKER_SECTION_TAGS}"
+            OUTPUT_BIN_NAMES    "${LINKER_OUTPUT_BIN_TAGS}")
+
+    set(MPS4_FPGA_CONFIG "${CMAKE_CURRENT_SOURCE_DIR}/scripts/mps4/${TARGET_SUBSYSTEM}/images.txt")
+
+    add_custom_command(TARGET ${PARSED_TARGET_NAME}
+            POST_BUILD
+            COMMAND ${CMAKE_COMMAND} -E copy ${MPS4_FPGA_CONFIG} ${SECTORS_DIR})
+
+    # Add tests for application on FVP if FVP path specified
+    if (BUILD_FVP_TESTS)
+
+        # Build for all use cases if USE_SINGLE_INPUT as no telnet interaction required
+        # otherwise only build for inference runner
+        if ((USE_SINGLE_INPUT) OR (${use_case} STREQUAL "inference_runner"))
+            set(AXF_PATH "${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf")
+            set(TEST_TARGET_NAME "${use_case}_fvp_test")
+
+            message(STATUS "Adding FVP test for ${use_case}")
+
+            add_test(
+                NAME "${TEST_TARGET_NAME}"
+                COMMAND ${FVP_PATH} -a ${AXF_PATH}
+                    -C mps4_board.telnetterminal0.start_telnet=0
+                    -C mps4_board.uart0.out_file='-'
+                    -C mps4_board.uart0.shutdown_on_eot=1
+                    -C mps4_board.visualisation.disable-visualisation=1
+                    -C vis_hdlcd.disable_visualisation=1
+                    -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0x12000000
+                    --stat)
+        endif()
+    endif ()
+
+endfunction()
diff --git a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld
new file mode 100644
index 0000000..10ead0e
--- /dev/null
+++ b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld
@@ -0,0 +1,218 @@
+/*
+ * SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+__STACK_SIZE = 0x00008000;
+__HEAP_SIZE  = 0x000C0000;
+
+/* System memory brief */
+MEMORY
+{
+  ITCM  (rx)  : ORIGIN = 0x10000000, LENGTH = 0x00008000
+  DTCM  (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
+  BOOT  (rx)  : ORIGIN = 0x11000000, LENGTH = 0x00010000
+  BRAM  (rwx) : ORIGIN = 0x12000000, LENGTH = 0x00200000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
+
+  /* Dynamic load regions declared for use by FVP only
+   * These regions are mentioned in the CMake subsystem profile.
+   * Do not change the addresses here in isolation. */
+  DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+  DDR_dynamic_ifm   (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000
+  DDR_dynamic_ofm   (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions ITCM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text.at_bram :
+  {
+    KEEP(*(.vectors))
+    *(.text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    KEEP(*(.eh_frame*))
+
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+
+    *(.rodata*)
+    . = ALIGN(4);
+    * (npu_driver_version)
+    . = ALIGN(4);
+    * (npu_driver_arch_version)
+    . = ALIGN(4);
+
+    __copy_table_start__ = .;
+    . = ALIGN(4);
+    __copy_table_end__ = .;
+  } > BRAM
+
+  __exidx_start = .;
+  .ARM.exidx.at_bram :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > BRAM
+  __exidx_end = .;
+
+  .sram :
+  {
+    . = ALIGN(16);
+    /* Cache area (if used) */
+    *(.bss.NoInit.ethos_u_cache)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+    *(.bss.NoInit.activation_buf_sram)
+    . = ALIGN(16);
+  } > SRAM AT > SRAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > BRAM
+
+  .zero.table.at_bram :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+    LONG (__bss_start__)
+    LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */
+
+    __zero_table_end__ = .;
+  } > BRAM
+
+  .heap (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > BRAM
+
+  __bram_total = ALIGN(4);
+
+  ASSERT( __bram_total < (ORIGIN(BRAM) + LENGTH(BRAM)), "BRAM overflow")
+
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM
+  PROVIDE(__stack = __StackTop);
+  ASSERT(__STACK_SIZE <= LENGTH(DTCM), "DTCM overflow")
+
+  .ddr.at_ddr :
+  {
+    /* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
+     * Force the alignment here as a workaround */
+    . = ALIGN(16);
+    /* nn model's baked in input matrices */
+    *(ifm)
+    . = ALIGN(16);
+    /* nn model's default space */
+    *(nn_model)
+    . = ALIGN (16);
+    /* labels */
+    *(labels)
+    . = ALIGN (16);
+    *Labels*.obj (*.rodata*)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+    *(activation_buf_dram)
+    . = ALIGN (16);
+  } > DDR AT > DDR
+
+}
diff --git a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct
new file mode 100644
index 0000000..4451f21
--- /dev/null
+++ b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct
@@ -0,0 +1,143 @@
+;  SPDX-FileCopyrightText: Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+;  SPDX-License-Identifier: Apache-2.0
+;
+;  Licensed under the Apache License, Version 2.0 (the "License");
+;  you may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at
+;
+;      http://www.apache.org/licenses/LICENSE-2.0
+;
+;  Unless required by applicable law or agreed to in writing, software
+;  distributed under the License is distributed on an "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+
+; *************************************************************
+; ***       Scatter-Loading Description File                ***
+; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping
+; information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should
+;       only be placed in those regions.
+;
+
+;---------------------------------------------------------
+; First load region (FPGA SRAM) 2MiB region
+; NOTE: The default INITSVTOR is 0x11000000 and not the
+; ITCM (32K) which we do not use for any code, but
+; could potentially put some critical code in there
+; if we need to.
+; @TODO: The memory pointed to by the INITSVTOR is a 64
+;        kiB location for boot code which we should use.
+;---------------------------------------------------------
+LOAD_REGION_0       0x12000000                  0x00200000
+{
+    ;-----------------------------------------------------
+    ; First 640K of FGPA SRAM.
+    ;-----------------------------------------------------
+    bram.bin        0x12000000                  0x000A0000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections)
+
+        ; Essentially only RO (code + data)
+        .ANY (+RO)
+    }
+
+    ;-----------------------------------------------------
+    ; Next 384K of SRAM/BRAM region for RO, RW and ZI
+    ; data, 8 byte aligned.
+    ;-----------------------------------------------------
+    data.bin        0x120A0000 ALIGN 8          0x00060000
+    {
+        ; Any RO-DATA
+        .ANY (+RO-DATA)
+
+        ; Any R/W and/or zero initialised data
+        .ANY(+RW +ZI)
+    }
+
+    ;-----------------------------------------------------
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
+    ;-----------------------------------------------------
+    ARM_LIB_HEAP    0x12100000 EMPTY ALIGN 8    0x000C0000
+    {}
+
+    ;-----------------------------------------------------
+    ; 32 kiB of stack space occupying the DTCM region.
+    ;-----------------------------------------------------
+    ARM_LIB_STACK   0x30000000 EMPTY ALIGN 8    0x00008000
+    {}
+
+    ;-----------------------------------------------------
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers. The total memory is 4 MiB (we are choosing
+    ; to not use the other bank). This region should have
+    ; 3 cycle read latency from both CPU and Ethos-U NPU.
+    ;-----------------------------------------------------
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
+    {
+        ; Cache area (if used)
+        *.o (.bss.NoInit.ethos_u_cache)
+
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
+        *.o (.bss.NoInit.activation_buf_sram)
+    }
+}
+
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x70000000                  0x02000000
+{
+    ;-----------------------------------------------------
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
+    ;-----------------------------------------------------
+    ddr.bin        0x70000000 ALIGN 16         0x02000000
+    {
+        ; nn model's baked in input matrices
+        *.o (ifm)
+
+        ; nn model's default space
+        *.o (nn_model)
+
+        ; labels
+        *.o (labels)
+        Labels.o (+RO-DATA)
+
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (activation_buf_dram)
+    }
+
+    ;-----------------------------------------------------
+    ; The following regions are for use by the FVP to
+    ; allow loading or dumping of dynamic data into or
+    ; from the memory. These regions are mentioned in
+    ; the CMake subsystem profile. Do not change the
+    ; addresses and sizes below in isolation.
+    ;-----------------------------------------------------
+    ; 32 MiB of model space for run-time load of model
+    ;-----------------------------------------------------
+    runtime_model   0x90000000 EMPTY ALIGN 16   0x02000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of IFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ifm     0x92000000 EMPTY ALIGN 16   0x01000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of OFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ofm     0x93000000 EMPTY ALIGN 16   0x01000000
+    {}
+}
diff --git a/scripts/cmake/platforms/platforms-preset.json b/scripts/cmake/platforms/platforms-preset.json
index 7a96d7a..b38739c 100644
--- a/scripts/cmake/platforms/platforms-preset.json
+++ b/scripts/cmake/platforms/platforms-preset.json
@@ -8,7 +8,7 @@
     "configurePresets": [
         {
             "name": "mps3-300-platform",
-            "description": "Target mps3 board, SSE-300 subsystem.",
+            "description": "Target MPS3 board, SSE-300 subsystem.",
             "hidden": true,
             "cacheVariables": {
                 "TARGET_PLATFORM": {
@@ -23,7 +23,7 @@
         },
         {
             "name": "mps3-310-platform",
-            "description": "Target mps3 board, SSE-310 subsystem.",
+            "description": "Target MPS3 board, SSE-310 subsystem.",
             "hidden": true,
             "cacheVariables": {
                 "TARGET_PLATFORM": {
@@ -37,6 +37,21 @@
             }
         },
         {
+            "name": "mps4-315-platform",
+            "description": "Target MPS4 board, SSE-315 subsystem.",
+            "hidden": true,
+            "cacheVariables": {
+                "TARGET_PLATFORM": {
+                    "type": "STRING",
+                    "value": "mps4"
+                },
+                "TARGET_SUBSYSTEM": {
+                    "type": "STRING",
+                    "value": "sse-315"
+                }
+            }
+        },
+        {
             "name": "simple-platform",
             "description": "Target simple platform.",
             "hidden": true,