MLECO-2985 Adding Corstone-310 support

Change-Id: Ifa4b11154478355c10cb3e747b9938a74afd242b
Signed-off-by: Eanna O Cathain <eanna.ocathain@arm.com>

4 files changed, 50 insertions, 9 deletions

diff --git a/docs/sections/appendix.md b/docs/sections/appendix.md
index 555560f..46b838a 100644
--- a/docs/sections/appendix.md
+++ b/docs/sections/appendix.md
@@ -6,15 +6,33 @@ The following table refers to the memory mapping information specific to the Arm
 
 | Name  | Base address | Limit address |  Size     | IDAU |  Remarks                                                  |
 |-------|--------------|---------------|-----------|------|-----------------------------------------------------------|
-| ITCM  | 0x0000_0000  |  0x0007_FFFF  |   512 kiB |  NS  |   ITCM code region                                        |
-| BRAM  | 0x0100_0000  |  0x0120_0000  |   2 MiB   |  NS  |   FPGA data SRAM region                                   |
+| ITCM  | 0x0000_0000  |  0x0007_FFFF  |  512 kiB  |  NS  |   ITCM code region                                        |
+| BRAM  | 0x0100_0000  |  0x0110_0000  |   1 MiB   |  NS  |   FPGA data SRAM region                                   |
 | DTCM  | 0x2000_0000  |  0x2007_FFFF  |  512 kiB  |  NS  |   4 banks for 128 kiB each                                |
-| SRAM  | 0x2100_0000  |  0x213F_FFFF  |  4 MiB    |  NS  |   2 banks of 2 MiB each as SSE-300 internal SRAM region   |
+| SRAM  | 0x2100_0000  |  0x2120_0000  |   2 MiB   |  NS  |   2 banks of 1 MiB each as SSE-300 internal SRAM region   |
 | DDR   | 0x6000_0000  |  0x6FFF_FFFF  |   256 MiB |  NS  |   DDR memory region                                       |
 | ITCM  | 0x1000_0000  |  0x1007_FFFF  |   512 kiB |  S   |   ITCM code region                                        |
-| BRAM  | 0x1100_0000  |  0x1120_0000  |   2 MiB   |  S   |   FPGA data SRAM region                                   |
+| BRAM  | 0x1100_0000  |  0x1110_0000  |   1 MiB   |  S   |   FPGA data SRAM region                                   |
 | DTCM  | 0x3000_0000  |  0x3007_FFFF  |   512 kiB |  S   |   4 banks for 128 kiB each                                |
-| SRAM  | 0x3100_0000  |  0x313F_FFFF  |   4 MiB   |  S   |   2 banks of 2 MiB each as SSE-300 internal SRAM region   |
+| SRAM  | 0x3100_0000  |  0x3120_0000  |   2 MiB   |  S   |   2 banks of 1 MiB each as SSE-300 internal SRAM region   |
 | DDR   | 0x7000_0000  |  0x7FFF_FFFF  |  256 MiB  |  S   |   DDR memory region                                       |
 
 The default memory map can be found here: <https://developer.arm.com/documentation/101051/0002/Memory-model/Memory-map>.
+
+## Arm® Cortex®-M55 Memory map overview for Corstone™-310 reference design
+
+The following table refers to the memory mapping information specific to the Arm® Cortex®-M55.
+
+| Name  | Base address | Limit address |  Size     | IDAU |  Remarks                                                  |
+|-------|--------------|---------------|-----------|------|-----------------------------------------------------------|
+| ITCM  | 0x0000_0000  |  0x0000_7FFF  |   32 kiB  |  NS  |   ITCM code region                                        |
+| BRAM  | 0x0100_0000  |  0x0120_0000  |   2 MiB   |  NS  |   FPGA data SRAM region                                   |
+| DTCM  | 0x2000_0000  |  0x2000_7FFF  |   32 kiB  |  NS  |   4 banks for 8 kiB each                                  |
+| SRAM  | 0x2100_0000  |  0x213F_FFFF  |   4 MiB   |  NS  |   2 banks of 2 MiB each as SSE-310 internal SRAM region   |
+| DDR   | 0x6000_0000  |  0x6FFF_FFFF  |   256 MiB |  NS  |   DDR memory region                                       |
+| ITCM  | 0x1000_0000  |  0x1000_7FFF  |   32 kiB  |  S   |   ITCM code region                                        |
+| BRAM  | 0x1100_0000  |  0x1120_0000  |   2 MiB   |  S   |   FPGA data SRAM region                                   |
+| DTCM  | 0x3000_0000  |  0x3000_7FFF  |   32 kiB  |  S   |   4 banks for 8 kiB each                                  |
+| SRAM  | 0x3100_0000  |  0x313F_FFFF  |   4 MiB   |  S   |   2 banks of 2 MiB each as SSE-310 internal SRAM region   |
+| DDR   | 0x7000_0000  |  0x7FFF_FFFF  |  256 MiB  |  S   |   DDR memory region                                       |
+
diff --git a/docs/sections/arm_virtual_hardware.md b/docs/sections/arm_virtual_hardware.md
index 23c21c4..47761ee 100644
--- a/docs/sections/arm_virtual_hardware.md
+++ b/docs/sections/arm_virtual_hardware.md
@@ -35,7 +35,10 @@ You can find more information about Arm Virtual Hardware [here](https://arm-soft
 
 Once you have access to the AWS instance, we recommend starting from the
 [quick start guide](../quick_start.md#Quick-start-example-ML-application) in order to get familiar
-with the ml-embedded-evaluation-kit. Note that on the AWS instance, the FVP is available under `/opt/FVP_Corstone_SSE-300`.
+with the ml-embedded-evaluation-kit. Note that on the AWS instance, the FVPs are available under:
+ - `/opt/VHT/VHT_Corstone_SSE-300_Ethos-U55`
+ - `/opt/VHT/VHT_Corstone_SSE-300_Ethos-U65`
+ - `/opt/VHT/VHT_Corstone_SSE-310`
 
 In order to view the FVP window when launching on the AWS instance a VNC is required.
 See relevant section [here](https://aws.amazon.com/premiumsupport/knowledge-center/ec2-linux-2-install-gui/).
diff --git a/docs/sections/building.md b/docs/sections/building.md
index 5f8a3cb..8fe9f8a 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -15,6 +15,7 @@
       - [Using Arm Compiler](./building.md#using-arm-compiler)
       - [Generating project for Arm Development Studio](./building.md#generating-project-for-arm-development-studio)
       - [Configuring with custom TPIP dependencies](./building.md#configuring-with-custom-tpip-dependencies)
+    - [Configuring the build for MPS3 SSE-310](./building.md#configuring-the-build-for-mps3-sse_310)
     - [Configuring native unit-test build](./building.md#configuring-native-unit_test-build)
     - [Configuring the build for simple-platform](./building.md#configuring-the-build-for-simple_platform)
     - [Building the configured project](./building.md#building-the-configured-project)
@@ -62,14 +63,14 @@ Before proceeding, it is *essential* to ensure that the following prerequisites
 
 - If you are using the proprietary Arm Compiler, ensure that the compiler license has been correctly configured.
 
-- CMake version 3.15.6 or above is installed and available on the path. Test CMake by running:
+- CMake version 3.16.3 or above is installed and available on the path. Test CMake by running:
 
     ```commandline
     cmake --version
     ```
 
     ```log
-    cmake version 3.16.2
+    cmake version 3.16.3
     ```
 
 > **Note:** How to add cmake to the path:
@@ -159,6 +160,7 @@ The build parameters are:
 - `TARGET_SUBSYSTEM`: The target platform subsystem. Specifies the design implementation for the deployment target. For
   both, the MPS3 FVP and the MPS3 FPGA, this must be left to the default value of SSE-300:
   - `sse-300` (default - [Arm® Corstone™-300](https://developer.arm.com/ip-products/subsystem/corstone/corstone-300))
+  - `sse-310` (The FVP is available via Arm Virtual Hardware (AVH) hosted on AWS)
 
 - `CMAKE_TOOLCHAIN_FILE`: This built-in CMake parameter can be used to override the default toolchain file used for the
   build. All the valid toolchain files are located in the scripts directory. For example, see:
@@ -471,6 +473,24 @@ cmake .. \
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
 
+
+### Configuring the build for MPS3 SSE-310
+
+On Linux, execute the following command to build the application for target platform `mps3` and subsystem `sse-310`,
+using the default toolchain file for the target as `bare-metal-gcc` and the default *Ethos-U55* timing adapter settings.
+This is equivalent to running:
+
+```commandline
+cmake .. \
+    -DCMAKE_TOOLCHAIN_FILE=scripts/cmake/toolchains/bare-metal-gcc.cmake \
+    -DTARGET_PLATFORM=mps3 \
+    -DTARGET_SUBSYSTEM=sse-310 \
+    -DTA_CONFIG_FILE=scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake
+```
+
+> **Note:** Only *Ethos-U55* timing adapter settings can be used.
+> *Ethos-U65* is not supported for this subsystem.
+
 ### Configuring native unit-test build
 
 ```commandline
diff --git a/docs/sections/deployment.md b/docs/sections/deployment.md
index 84ffcf6..e2600d8 100644
--- a/docs/sections/deployment.md
+++ b/docs/sections/deployment.md
@@ -205,7 +205,7 @@ size, you must use the following approach:
 
     Note that the `itcm.bin` and `ddr.bin` files correspond to the part of the application residing in the first and
     second load region respectively, as defined in the
-    [scatter file](../../scripts/cmake/platforms/mps3/mps3-sse-300.sct).
+    [scatter file](../../scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct).
 
 2. The `./bin/sectors/images.txt` file must be copied over to the MPS3. The exact location for the destination depends
    on the version of the MPS3 board and the application note for the bit file in use.