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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2022-04-01 14:43:53 +0100 |
|---|---|---|
| committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2022-04-05 09:30:23 +0100 |
| commit | da2ec067da418d3d80b2829b111df25bd901eb5c (patch) | |
| tree | 0ccba5c7655ad042bd21f71ffd59c0f52c163f62 /docs/sections/building.md | |
| parent | 8bc863dd6a7d0937aa66df655a7fe0e235dd2d4f (diff) | |
| download | ml-embedded-evaluation-kit-da2ec067da418d3d80b2829b111df25bd901eb5c.tar.gz | |
MLECO-3096: Removing "timer" from HAL profile.
Attempting to have timer functionality contained within
the platform drivers "package" as it should (in line with
the refactoring work done so far under HAL). This will
ensure that we don't need two timer implementations under
HAL "profiles" and therefore, this whole directory can be
removed.
This change also addressed issue with the applicatio level
Profiler code knowing about how the PMU has been set up by
the platform code. This link has been removed completely.
This will make it much easier to add/amend the Ethos-U PMU
event counters types and give each platform the capability
of populating their relvant counters. The application level
Profiler doesn't know which metrics it is displaying but
just calculates and maintains statistics for whatever PMU
counters it receives from the HAL level.
A fix for timing adapter issue introduced in the last CR
is also included.
Change-Id: Ia46e03a06e7b8e42b9ed2ba8f2af2dcd2229c110
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Diffstat (limited to 'docs/sections/building.md')
| -rw-r--r-- | docs/sections/building.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/sections/building.md b/docs/sections/building.md index 699667b..5f8a3cb 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -206,7 +206,7 @@ The build parameters are: `ETHOS_U_NPU_ID` is `U65`. Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). - `CPU_PROFILE_ENABLED`: Sets whether profiling information for the CPU core should be displayed. By default, this is - set to false, but can be turned on for FPGA targets. The the FVP and the CPU core cycle counts are not meaningful and + set to false, but can be turned on for FPGA targets. The FVP and the CPU core cycle counts are **not** meaningful and are not to be used. - `LOG_LEVEL`: Sets the verbosity level for the output of the application over `UART`, or `stdout`. Valid values are: |