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authorLouis Verhaard <louis.verhaard@arm.com>2021-03-11 14:59:06 +0100
committerLouis Verhaard <louis.verhaard@arm.com>2021-03-16 10:37:20 +0100
commitc822d62ba27b874a130e9d8d434c12b419d10d62 (patch)
tree4450a032513b537ffd3545cb2bdb6e052339beb2 /SUPPORTED_OPS.md
parent8ba0792731d47de64a59d93359340f3c88fc4a62 (diff)
downloadethos-u-vela-c822d62ba27b874a130e9d8d434c12b419d10d62.tar.gz
MLBEDSW-4223: Full support for PAD operator
- Added full support for PAD operator - Hardware padding is still used whenever possible - Bug fix Pad followed by max pool if IFM contains negative values Change-Id: Ifc64d1943737d94466f5e2821009dab12a49a965 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
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# Supported Ops
This file was automatically generated by Vela using the `--supported-ops-report` parameter.
-Vela version: `2.1.0`
+Vela version: `2.1.2.dev0+g41c006a.d20210309`
This file complies with
[**Gitiles Markdown syntax**](https://github.com/google/gitiles/blob/master/Documentation/markdown.md)
@@ -239,15 +239,11 @@ This is a list of constraints that the MUL operator must satisfy in order to be
This is a list of constraints that the PAD operator must satisfy in order to be scheduled on the NPU.
-- IFM and OFM data types must match
-- Both Input quantization parameters must match OFM quantization parameters
- Number of input tensors must be exactly 2
-- The padding tensor must have the shape [4,2]
+- The padding tensor must have the shape [3,2] or [4,2]
- The pad tensor can only pad width and height
- Pad tensor must be of type: int32, int64
- The padding tensor must be constant
-- Must be followed by one of the following operator types: AVERAGE_POOL_2D, CONV_2D, DEPTHWISE_CONV_2D, MAX_POOL_2D
-- Padding must be at most kernel size divided by 2
## RESIZE_BILINEAR Constraints