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| author | Johan Alfven <johan.alfven@arm.com> | 2023-02-14 15:20:03 +0100 |
|---|---|---|
| committer | tim.hall <tim.hall@arm.com> | 2023-02-15 18:35:28 +0000 |
| commit | bfe6fe31cc462b8e3a9435f463835f2714da1903 (patch) | |
| tree | f434596481b21514e43d687c74bf94481caf71c1 | |
| parent | d0e41cf4c20a0f5780a8dd072df29bdb3267d960 (diff) | |
| download | ethos-u-vela-bfe6fe31cc462b8e3a9435f463835f2714da1903.tar.gz | |
MLBEDSW-7347: MLCE: Split followed by elementwise op will assert
- The problem was that when the split slice read was moved
to the tensor consumer, in this case an elementwise operator,
this was not taken into account when the npu op for the
element wise operator was created. The npu op was created
with wrong ifm_width and ifm and ifm2 ended up with different
sizes. As a result, broadcasting is expected but that is
not True so the assert was triggered.
- The fix is to use the ifm box in order to set the correct
ifm_width for the npu operator.
Change-Id: I3291d34e7f8e7add9caf2296cca600c60e96bf7e
Signed-off-by: Johan Alfven <johan.alfven@arm.com>
| -rw-r--r-- | ethosu/vela/high_level_command_to_npu_op.py | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/ethosu/vela/high_level_command_to_npu_op.py b/ethosu/vela/high_level_command_to_npu_op.py index fe1c9f8a..2c62c6f7 100644 --- a/ethosu/vela/high_level_command_to_npu_op.py +++ b/ethosu/vela/high_level_command_to_npu_op.py @@ -1,4 +1,4 @@ -# SPDX-FileCopyrightText: Copyright 2020-2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2020-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> # # SPDX-License-Identifier: Apache-2.0 # @@ -475,7 +475,7 @@ def set_common_op_fields(npu_op: NpuBlockOperation, cmd: NpuStripe, arch: Archit op = ps.primary_op ifm_height = cmd.ifm_box.get_block().height - ifm_width = cmd.ps.ifm_shapes[0].width + ifm_width = cmd.ifm_box.get_block().width ifm_depth = get_ifm_depth(op.type.npu_block_type, cmd.ifm_box, cmd.ofm_box) npu_op.ifm = create_feature_map(cmd.ifm_tensor, cmd.ifm_box, arch, ps.ifm_shapes[0], op.tile_base_offsets_ifm[0]) @@ -579,8 +579,7 @@ def create_npu_elementwise_op(cmd: NpuStripe, arch: ArchitectureFeatures) -> Npu npu_op.ifm2.shape = NpuShape3D(height=0, width=0, depth=0) else: ifm2_blk = cmd.ifm2_box.get_block() - ifm2_width = ps.ifm_shapes[1].width - npu_op.ifm2.shape = NpuShape3D(height=ifm2_blk.height, width=ifm2_width, depth=ifm2_blk.depth) + npu_op.ifm2.shape = NpuShape3D(height=ifm2_blk.height, width=ifm2_blk.width, depth=ifm2_blk.depth) set_common_op_fields(npu_op, cmd, arch) # Check if output scale needs to be overridden output_scale = None |