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| author | Mikael Olsson <mikael.olsson@arm.com> | 2023-09-11 14:01:58 +0200 |
|---|---|---|
| committer | Mikael Olsson <mikael.olsson@arm.com> | 2023-09-15 10:51:06 +0200 |
| commit | 3875fa7e48e302efc0a8e2f6dbacd9c321a9884d (patch) | |
| tree | 31422c2774471f5d1d5f1b0a3d2a228c5ef45612 | |
| parent | 6fb238f4a2fe1592275449c419b5140c9eb9dd49 (diff) | |
| download | ethos-u-linux-driver-stack-3875fa7e48e302efc0a8e2f6dbacd9c321a9884d.tar.gz | |
Fix code style in Juno FPGA reset driver
There were some places in the Juno FPGA reset driver that did not follow
the Linux kernel code style which have now been fixed.
Change-Id: I0316b23b99fde05068ba5e50442a6cb5b5ea8214
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
| -rw-r--r-- | remoteproc/juno_fpga_reset.c | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/remoteproc/juno_fpga_reset.c b/remoteproc/juno_fpga_reset.c index fab90cf..29b2eb9 100644 --- a/remoteproc/juno_fpga_reset.c +++ b/remoteproc/juno_fpga_reset.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-License-Identifier: GPL-2.0-only * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -14,8 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, you can access it online at * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0-only */ #include <linux/io.h> @@ -55,21 +54,23 @@ static void __iomem *verify_and_remap(struct device *dev, id = readl(JUNO_FPGA_RESET_ID(base)); if (id != 0x2010f && - id != 0x20110 && - id != 0x20111 && - id != 0x20112) { - dev_err(dev, "ID not matching"); + id != 0x20110 && + id != 0x20111 && + id != 0x20112) { + dev_err(dev, "ID not matching"); + return IOMEM_ERR_PTR(-EINVAL); - } + } return base; } int juno_fpga_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) + unsigned long id) { - struct juno_fpga_reset *reset = container_of(rcdev, struct juno_fpga_reset, - rst); + struct juno_fpga_reset *reset = container_of(rcdev, + struct juno_fpga_reset, + rst); /* pull reset */ dev_dbg(reset->dev, "Asserting reset"); @@ -82,20 +83,23 @@ int juno_fpga_reset_assert(struct reset_controller_dev *rcdev, writel(JUNO_FPGA_RESET_UNSET_RESET, JUNO_FPGA_RESET_SOFT_RESET(reset->base)); + return 0; } int juno_fpga_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) + unsigned long id) { - struct juno_fpga_reset *reset = container_of(rcdev, struct juno_fpga_reset, - rst); + struct juno_fpga_reset *reset = container_of(rcdev, + struct juno_fpga_reset, + rst); /* release wait */ dev_dbg(reset->dev, "Deasserting reset"); writel(JUNO_FPGA_RESET_UNSET_CPUWAIT, JUNO_FPGA_RESET_CPU_WAIT(reset->base)); + return 0; } @@ -125,9 +129,11 @@ static int juno_fpga_reset_probe(struct platform_device *pdev) reset->dev = dev; if (IS_ERR(reset->base)) { - dev_err(dev, "Failed to verify and remap base address (%ld)", PTR_ERR(reset->base)); + dev_err(dev, "Failed to verify and remap base address (%ld)", + PTR_ERR(reset->base)); + return PTR_ERR(reset->base); - } + } platform_set_drvdata(pdev, reset); |