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-rw-r--r--targets/corstone-300/platform.ld27
1 files changed, 22 insertions, 5 deletions
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld
index 8d44c1b..ec58acc 100644
--- a/targets/corstone-300/platform.ld
+++ b/targets/corstone-300/platform.ld
@@ -65,6 +65,16 @@
* memory banks.
*/
+#ifndef ETHOSU_MODEL
+ /* default value - '1', for DRAM */
+ #define ETHOSU_MODEL 1
+#endif
+
+#ifndef ETHOSU_ARENA
+ /* default value - '1', for DRAM */
+ #define ETHOSU_ARENA 1
+#endif
+
__STACK_SIZE = 0x00008000;
__HEAP_SIZE = 0x00008000;
@@ -239,25 +249,32 @@ SECTIONS
.sram.bss :
{
. = ALIGN(16);
-#ifdef ETHOSU_FAST_MEMORY_SIZE
- *(.bss.ethosu_scratch);
-#else
+#if (ETHOSU_MODEL == 0)
+ * (network_model_sec)
+#endif
+
+#if (ETHOSU_ARENA == 0)
*(.bss.tensor_arena)
#endif
+
+ *(.bss.ethosu_scratch);
*.(output_data_sec)
} > SRAM :null
.ddr :
{
-#ifdef ETHOSU_FAST_MEMORY_SIZE
+#if (ETHOSU_ARENA == 1)
. = ALIGN(16);
*(.bss.tensor_arena)
#endif
+
. = ALIGN(4);
*(input_data_sec)
. = ALIGN(16);
+#if (ETHOSU_MODEL == 1)
*(network_model_sec)
- *(expected_output_data_sec)
+#endif
+ * (expected_output_data_sec)
} > DDR :rom_dram
__eddr_data = ALIGN (16) ;