diff options
| author | Davide Grohmann <davide.grohmann@arm.com> | 2022-06-15 11:20:41 +0200 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-08-25 09:13:36 +0000 |
| commit | f4379e99431e5b027b0d5942ccff56af6bfe82b1 (patch) | |
| tree | 793dbd611483e6850dfc29db3048f92975800bf8 /targets | |
| parent | 05dd24dd63fcd0a2f8d6a0db1a7bf740ee968a00 (diff) | |
| download | ethos-u-core-platform-f4379e99431e5b027b0d5942ccff56af6bfe82b1.tar.gz | |
Add negative testing to message_handler
Also restructure the scatter file to not be constrained of the
artificial 512k size limit of the APP_IMAGE region.
Add missing sections in DDR for both scatter file and linker script.
Change-Id: I3d9bc8aeae1b1c11ab994276be64a2850cc23f8e
Diffstat (limited to 'targets')
| -rw-r--r-- | targets/corstone-300/platform.ld | 4 | ||||
| -rw-r--r-- | targets/corstone-300/platform.scatter | 41 |
2 files changed, 29 insertions, 16 deletions
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index 12cc6ee..d22b786 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -278,6 +278,10 @@ SECTIONS *(network_model_sec) #endif * (expected_output_data_sec) + * (sec_command_stream, sec_weight_data, sec_input_data) + + * (ethosu_core_in_queue) + * (ethosu_core_out_queue) . = ALIGN(4); } > DDR :rom_dram diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index 55e21b7..d683100 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -144,6 +144,25 @@ APP_IMAGE LR_START LR_SIZE .ANY (+RO) } + ; DTCM 512kB + ; Only accessible from the Cortex-M + DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE) + { + .ANY1 (+RW +ZI) + } + + ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} + ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {} + +#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { + ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +LOAD_REGION_BRAM BRAM_START BRAM_SIZE +{ #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) ; MPS3 BRAM ; Shared between Cortex-M and the NPU @@ -163,14 +182,10 @@ APP_IMAGE LR_START LR_SIZE * (.sram.data) } #endif +} - ; DTCM 512kB - ; Only accessible from the Cortex-M - DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE) - { - .ANY1 (+RW +ZI) - } - +LOAD_REGION_SRAM SRAM_START SRAM_SIZE +{ ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55 SRAM SRAM_START SRAM_SIZE { @@ -187,15 +202,6 @@ APP_IMAGE LR_START LR_SIZE ; Place scratch buffer in SRAM * (.bss.ethosu_scratch) } - - ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} - ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {} - -#if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) - STACKSEAL +0 EMPTY __STACKSEAL_SIZE { - ; Reserve empty region for stack seal immediately after stack - } -#endif } LOAD_REGION_1 DDR_START DDR_SIZE @@ -215,6 +221,9 @@ LOAD_REGION_1 DDR_START DDR_SIZE * (expected_output_data_sec) * (output_data_sec) * (sec_command_stream, sec_weight_data, sec_input_data) + + * (ethosu_core_in_queue) + * (ethosu_core_out_queue) } #if (ETHOSU_ARENA == 1) |