blob: d6628865e4af7ce6b6f584eeeee37b133cc8b080 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*
* Copyright (c) 2019-2020,2022 Arm Limited.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ETHOSU_CONFIG_H
#define ETHOSU_CONFIG_H
/* Set default values if not manually overriden */
#ifndef NPU_QCONFIG
#define NPU_QCONFIG 2
#endif
#ifndef NPU_REGIONCFG_0
#define NPU_REGIONCFG_0 3
#endif
#ifndef NPU_REGIONCFG_1
#define NPU_REGIONCFG_1 2
#endif
#ifndef NPU_REGIONCFG_2
#define NPU_REGIONCFG_2 1
#endif
#ifndef NPU_REGIONCFG_3
#define NPU_REGIONCFG_3 1
#endif
#ifndef NPU_REGIONCFG_4
#define NPU_REGIONCFG_4 1
#endif
#ifndef NPU_REGIONCFG_5
#define NPU_REGIONCFG_5 1
#endif
#ifndef NPU_REGIONCFG_6
#define NPU_REGIONCFG_6 1
#endif
#ifndef NPU_REGIONCFG_7
#define NPU_REGIONCFG_7 1
#endif
#ifndef AXI_LIMIT0_MAX_BEATS_BYTES
#define AXI_LIMIT0_MAX_BEATS_BYTES 0x0
#endif
#ifndef AXI_LIMIT0_MEM_TYPE
#define AXI_LIMIT0_MEM_TYPE 0x0
#endif
#ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS
#define AXI_LIMIT0_MAX_OUTSTANDING_READS 64
#endif
#ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES
#define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 32
#endif
#ifndef AXI_LIMIT1_MAX_BEATS_BYTES
#define AXI_LIMIT1_MAX_BEATS_BYTES 0x0
#endif
#ifndef AXI_LIMIT1_MEM_TYPE
#define AXI_LIMIT1_MEM_TYPE 0x0
#endif
#ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS
#define AXI_LIMIT1_MAX_OUTSTANDING_READS 64
#endif
#ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES
#define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 32
#endif
#ifndef AXI_LIMIT2_MAX_BEATS_BYTES
#define AXI_LIMIT2_MAX_BEATS_BYTES 0x0
#endif
#ifndef AXI_LIMIT2_MEM_TYPE
#define AXI_LIMIT2_MEM_TYPE 0x0
#endif
#ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS
#define AXI_LIMIT2_MAX_OUTSTANDING_READS 64
#endif
#ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES
#define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 32
#endif
#ifndef AXI_LIMIT3_MAX_BEATS_BYTES
#define AXI_LIMIT3_MAX_BEATS_BYTES 0x0
#endif
#ifndef AXI_LIMIT3_MEM_TYPE
#define AXI_LIMIT3_MEM_TYPE 0x0
#endif
#ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS
#define AXI_LIMIT3_MAX_OUTSTANDING_READS 64
#endif
#ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES
#define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 32
#endif
/*
* Address offset between the CPU and the NPU. The offset is
* applied to the QBASE and BASEP registers.
*/
#ifndef BASE_POINTER_OFFSET
#define BASE_POINTER_OFFSET 0
#endif
#endif /* #ifndef ETHOSU_CONFIG_H */
|
