Add driver async API

Add an asynchronous API to the driver. The current synchronous API
is now using the new async API internally. The main new functions
are ethosu_invoke_async() and ethosu_wait(). Every successfull call
to ethosu_invoke_async() must be followed by a call to ethosu_wait()
to get the status of the inference. The wait function can be called
in a blocking or non-blocking mode by specifying the `block`
argument to true/false. The regular synchronous invoke function is
implemented as a invoke_async followed by a wait(block=true) call.

Short sommary of changes:
 - Add an internal ethosu_job struct to keep track of
   inference data and job state.
 - Use async API in blocking mode for normal flow
 - Change default semaphore implementation to binary type
 - Move error prints out of interrupt context
 - Move ethosu_inference_begin() callback to right before HW invoke
 - Always call ethosu_inference_end() callback, even in case of errors
 - On NPU error, do not keep NPU powered after being reset

Change-Id: If4c3c46e3c6732a669e17251bd848dea5765a490

1 files changed, 12 insertions, 12 deletions

diff --git a/src/ethosu_device_u55_u65.c b/src/ethosu_device_u55_u65.c
index 9a92f63..31379fc 100644
--- a/src/ethosu_device_u55_u65.c
+++ b/src/ethosu_device_u55_u65.c
@@ -133,11 +133,11 @@ enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev)
     return ETHOSU_SUCCESS;
 }
 
-enum ethosu_error_codes ethosu_dev_run_command_stream(struct ethosu_device *dev,
-                                                      const uint8_t *cmd_stream_ptr,
-                                                      uint32_t cms_length,
-                                                      const uint64_t *base_addr,
-                                                      int num_base_addr)
+void ethosu_dev_run_command_stream(struct ethosu_device *dev,
+                                   const uint8_t *cmd_stream_ptr,
+                                   uint32_t cms_length,
+                                   const uint64_t *base_addr,
+                                   int num_base_addr)
 {
     assert(num_base_addr <= NPU_REG_BASEP_ARRLEN);
 
@@ -168,8 +168,14 @@ enum ethosu_error_codes ethosu_dev_run_command_stream(struct ethosu_device *dev,
 
     dev->reg->CMD.word = cmd.word;
     LOG_DEBUG("CMD=0x%08x", cmd.word);
+}
 
-    return ETHOSU_SUCCESS;
+void ethosu_dev_print_err_status(struct ethosu_device *dev)
+{
+    LOG_ERR("NPU status=0x%08" PRIx32 ", qread=%" PRIu32 ", cmd_end_reached=%d",
+            dev->reg->STATUS.word,
+            dev->reg->QREAD.word,
+            dev->reg->STATUS.cmd_end_reached);
 }
 
 bool ethosu_dev_handle_interrupt(struct ethosu_device *dev)
@@ -185,12 +191,6 @@ bool ethosu_dev_handle_interrupt(struct ethosu_device *dev)
     if (dev->reg->STATUS.bus_status || dev->reg->STATUS.cmd_parse_error || dev->reg->STATUS.wd_fault ||
         dev->reg->STATUS.ecc_fault || !dev->reg->STATUS.cmd_end_reached)
     {
-        LOG_ERR("NPU fault. status=0x%08" PRIx32 ", qread=%" PRIu32 ", cmd_end_reached=%d",
-                dev->reg->STATUS.word,
-                dev->reg->QREAD.word,
-                dev->reg->STATUS.cmd_end_reached);
-        ethosu_dev_soft_reset(dev);
-        ethosu_dev_set_clock_and_power(dev, ETHOSU_CLOCK_Q_UNCHANGED, ETHOSU_POWER_Q_DISABLE);
         return false;
     }