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path: root/src/backends/reference/test/RefLayerTests.cpp
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2022-01-18MLCE-736 'Adding support for TfLite Models'Sadik Armagan
* Added constant input supports for Pack/Stack, Concatenation operators * Added Int32 support to Pack/Stack operator on CpuRef * Removed unsupported operator from TfLite Delegate Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I64203e174300d23eedeb22bddefe07e931c4eff3
2021-12-17IVGCVSW-6694 Disable long running Pooling3D unit test cases.Colm Donelan
* Disable the following test cases: LargeTensorsAveragePooling3d LargeTensorsAveragePooling3dUint8 LargeTensorsAveragePooling3dInt16 Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I908ce880b4d55598e913fc6b186f2bd2e796c613
2021-12-14IVGCVSW-6453 'Move the ArmNN Test Utils code to a physically separate directory'Sadik Armagan
* Created include/armnnTestUtils directory * Moved Arm NN test utils files into armnnTestUtils directory Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I03ac54c645c41c52650c4c03b6a58fb1481fef5d
2021-11-17IVGCVSW-6509 Front End + Reference Workload implementationTamás Nyíri
Subtask of story: IVGCVSW-6164 Add a Pooling3d FrontEnd and Ref Implementation * Add front end * Add reference workload * Add corresponding unit tests Change-Id: Icce4146dd0a06a1da46a2def00a82d343e171750 Signed-off-by: Tamas Nyiri <tamas.nyiri@arm.com>
2021-10-27IVGCVSW-6469 Add MirrorPad FrontEnd and Ref SupportMatthew Sloyan
* Added PaddingMode enum to PaddingDescriptor to enable Symmetric and Reflect padding. * Added Symmetric and Reflect Ref implementation. * Added Serializer & Deserializer support. * Added unit tests. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I4bed907b31742b32ccefe5e8ca39a6f1e5bd9dee
2021-10-20Add ConstTensorsAsInput support for Conv3dMatthew Sloyan
* Constant weights and biases are now stored as Constant layers. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteParser. * Updated Ref backend to handle constant weights and bias as inputs rather than reading from member variables. * Added Conv3d EndToEnd test. * Added NCDHW DataLayout and unit tests. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I10cdd354ca5f1c748730f92ffdb36bf810f83c8e
2021-10-01IVGCVSW-6163 Add Conv3d FrontEnd and Ref ImplementationMatthew Sloyan
* Added front-end * Added Reference workload * Added Serializer & Deserializer support * Added unit tests * Added NDHWC DataLayout Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Iec4d39e7433b5334d52fa44cf8efc6bcd39319d8
2021-09-30IVGCVSW-6293 Add Unit test int8 Channel ShuffleTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Icf69b4c707014c5ae76425ad326bd2826381f305
2021-09-24IVGCVSW-3705 Add Channel Shuffle Front end and Ref ImplementationSimon Obute
* Add front end * Add reference workload * Add unit tests * Add Serializer and Deserializer * Update ArmNN Versioning Signed-off-by: Simon Obute <simon.obute@arm.com> Change-Id: I9ac1f953af3974382eac8e8d62d794d2344e8f47
2021-09-03IVGCVSW-6262 Add support for Reduce ProdTeresa Charlin
* Tflite parser * Tflite delegate * Serializer * Deserializer * Ref, CpuAcc and GpuAcc workloads Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I601a9ee1680b372c7955d9a628857d08c3cfd377
2021-08-31MLCE-530 Add support of int8 weight for UnidirectionalSequenceLstmNarumol Prangnawarat
to Ref backend and armnn delegate Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I203d0029c12221228ffe229acda3c90594394e9b
2021-08-10MLCE-530 Add support for UnidirectionalSequenceLstm to RefWorkloadexperimental/daves_custom_allocator_dmabufNarumol Prangnawarat
* Add implementation of IsUnidirectionalSequenceLstmSupported to RefLayerSupport * Add RefUnidirectionalSequenceLstmWorkload * Refactor Lstm to be able to use for Lstm and SequenceLstm * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ibc066d213213a11b955dfefbe518de643298ba0c
2021-06-16MLCE-510 Add CpuRef Shape Operator to ArmNNKeith Davis
* Add front end * Add reference workload * Serialization/Deserialization * Add unit tests * Update ArmNN Versioning Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I6fcb1fa341d6f08dea4003b13544e6e9f53fefd3
2021-06-16IVGCVSW-6088 Add Sin and Log to ElementWiseUnaryTeresa Charlin
* Ref workload * Cl workload * Neon workload * Serializer * Deserializer * Remove boost include from TensorTest.cpp Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I498548169cc77609c55cf3105f1de5a7429772cf
2021-06-11IVGCVSW-5963 'Move unit tests to new framework'Sadik Armagan
* Used doctest in ArmNN unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ia9cf5fc72775878885c5f864abf2c56b3a935f1a
2021-06-02IVGCVSW-5962 Remove boost::multi_arraySadik Armagan
* Replaced all instances of boost::multi_array with flat vectors. * Updated LayerTestResult struct with new member variables. * Updated CompareTensor function to compare flat vectors and the shape. * Removed MakeTensor function from TensorHelpers.hpp. * Removed GetTensorShapeAsArray function from LayerTestResult.hpp. * Removed boost::array usage. * Removed boost::extents usages. * Removed boost::random usages. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iccde9d6640b534940292ff048fb80c00b38c4743
2021-04-12IVGCVSW-5410 Add front-end support for CASTmathad01
IVGCVSW-5415 Add TfLiteParser support for CAST * Added front end support for CAST, including support in the Reference workload, Serialization, Deserializtion, Unit tests, and TfLiteParser. Signed-off-by: mathad01 <matthew.haddon@arm.com> Change-Id: Iaf670ca5912a21ed6bc84f7f83a68b42154846bb
2021-03-25IVGCVSW-5736 and IVGCVSW-5743 'NonConstWeights: Update front-end and ↵Sadik Armagan
TfLiteDelegate support for FullyConnected Operator' * Added front-end support for non-const weights for FULLY_CONNECTED operator * Added FULLY_CONNECTED end-to-end test * Updated FULLY_CONNECTED operator support in TfLite Arm NN Delegate for non-const weights * Updated the version numbers Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iffa5b9aa9297aca4c02d923cce4636c88ac21faa
2021-02-09MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'Sadik Armagan
* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8
2021-02-03backends/reference: Add ReduceSum operation supportSadik Armagan
This patch addes ReduceSum operation support for reference backend, which computes the sum of elements across dimensions of a tensor. Changelog v1: - Fix file header descriptions. Chagelog v2: - Fix line limit issue. - Fix type conversion issue. Changelog v3: - Remove tabs. - Modify newly added file headers. Changelog v4: - Symbol on header isn't allowed so drop it from newly added file headers. Changelog v5: - Remove tabs, fix the use of brackets and align lines correctly. Changelog v6: - Add serializer and deserializer support. Changelog v7: - Fix build error add missed code. Changelog v8: - Rename ReduceSumDecriptor to ReduceDescriptor - Update m_KeepDims field data type to bool on ReduceDescriptor - Add ReduceOperation field to ReduceDescriptor - Rename ReduceSumLayer to ReduceLayer - Update ReduceLayer to use ReduceDescriptor - Update ReduceLayer::ValidateTensorShapesFromInputs() function - Rename RefReduceSumWokload to RefReduceWorkload - Update workload to use ReduceDescriptor - Update workload to use Decoders and Encoders - Remove ReduceSum.hpp and ReduceSum.cpp - Added Reduce.hpp and Reduce.cpp - Move Mean.cpp (which is implementing REDUCE_MEAN) functionality to Reduce.cpp - Update RefMeanWorkload to call Reduce function with ReduceOperation::Mean argument - Remove Mean.hpp and Mean.cpp - Update the Serializer/Deserializer ArmnnSchema.fbs for ReduceLayer, ReduceDescriptor, and ReduceOperation - Update Serializer and Deserializer for serializing/parsing ReduceLayer - Added TfLiter parser Sum test for REDUCE_SUM operator - Make corresponding changes on front-end and Ref backend to support REDUCE_SUM operator Changelog v9: - Fixed build errors. Change-Id: I8c8e034f3df73f9565b3c18eff51ecca6c542195 Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
2020-12-16IVGCVSW-5595 Fix incorrect padding value for asymmetric quantized typeNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I85f0c30757043f8c27c78d607f0f9dbbdd35b9fb
2020-11-18Fix logical vts skipNarumol Prangnawarat
* Add Boolean support for Reshape * Use LogicalUnary factory and data type for LogicalNot Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I8e072fde200b7716556ae67f79616458cf98ff20
2020-11-09IVGCVSW-5091 Add Logical ops frontend and ref implJames Conroy
* Add frontend and reference implementation for logical ops NOT, AND, OR. * Unary NOT uses existing ElementwiseUnary layer and ElementwiseUnary descriptor. * Binary AND/OR uses new layer LogicalBinary and new LogicalBinary descriptor. * Add serialization/deserializion support and add missing ElementwiseUnary deserializer code. * Add additional Boolean decoder in BaseIterator.hpp. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Id343b01174053a166de1b98b6175e04a5065f720
2020-08-31IVGCVSW-5256 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers Q,R & T Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I6fc613d31785298a0b7ed18f1abdd59bafed1e8e
2020-08-31IVGCVSW-5231 Remove CreateTensorHandle in the test where there is ↵Keith Davis
NO_DEPRECATE_WARN * Done for all elementwise layers, Activation, BatchNorm, BatchToSpace Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Id1d15a0960233026aecf7a07e0d3f006e07e4abf
2020-08-31IVGCVSW-5253 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers M-P Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I324eee7d750e30f714e0d346b7da7b69866ff935
2020-08-31IVGCVSW-5252 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers between G-L Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I197351a479fb211787bd12a73c9618d2ded95898
2020-08-31IVGCVSW-5249 Use CreateTensorHandle from ITensorHandleFactory in the test ↵Keith Davis
for all layers between C-D Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I9583adf50e67e63e73833f400d1c50fbff57f60c
2020-08-31IVGCVSW-5250 Remove CreateTensorHandle in the test for layers between E-FFinn Williams
* Refactored Floor and FullyConnected tests Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Iad87254e638bdcb5d7b334b16ec87a0c981e48a0
2020-08-28IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SplaceToDepth, Splitter, Stack and StridedSlice unit tests to use TensorHandleFactory for creating TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ib22bb09cd2120c02c548099eaa06db6e6f00b15e
2020-08-27IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SoftmaxTestImpl to use TensorHandleFactory to create TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I83559a89187bbed0d6f34ca589ea81c694bf5683
2020-08-27IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SpaceToBatchNd tests to use TensorHandleFactory to create TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I096a6e30ecc97dd9b93b206157f16d912085703c
2020-08-27IVGCVSW-5251 'Remove CreateTensorHandle for ArgMinMaxTestImpl'Sadik Armagan
* Refactored ArgMinMax tests to use TensorHandleFactory instead of WorkloadFactory Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ibff0f9370972f9a0a977c05275cb6168f8f88ae5
2020-08-26IVGCVSW-5250 Remove CreateTensorHandle in the test for layers between E-FFinn Williams
* Added new test function to pass in the ITensorHandleFactory Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I9b2e9250200e092541e29796ec53cabd0b677acf
2020-08-16IVGCVSW-5216 Remove CreateTensorHandle from TransposeTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iea9cc3a36021aac4b86ea5d8340dd8eb1f308283
2020-08-15IVGCVSW-5218 Remove CreateTensorHandle from DetectionPostProcess and PreluFrancis Murtagh
* Remove default arguments in Neon and CL causing ambiguity Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I314885719a16311b68c7bda37cd54b2ca0d14480
2020-07-30IVGCVSW-5174 Fix i386 Floor and AbsTestFrancis Murtagh
* Remove QSymm16 support for Floor to match NNApi and disable RefLayerTest * Return nullptr for floor workload if quantized type * Fix SimpleAbsTest incorrect output Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I80d9e2fb78777d0a3fc7ce6d12b5eb4af3fd1d3a
2020-07-24IVGCVSW-4889/IVGCVSW-4890 CL/Neon UnitTests for align_corners & half_pixelsTeresa Charlin
*Add more UnitTests to the reference implemenation. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Idbce68baa76b049e5f741f790a5cfd75acb54a95
2020-07-06IVGCVSW-4624 Add a RANK Reference ImplementationFinn Williams
* Add Rank front end * Add Rank reference implementation * Add Rank serialization support * Add Scalar serialization support Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I06e4a468c2a84e79bae2e6c5348596bbbf853b4b
2020-06-24IVGCVSW-4621 Add CL FILL WorkloadSadik Armagan
* Add CL workload for Fill Operator * Enabled Fill operator tests on CL * CLFill function does not have validate() function yet IsLayerSupported() function return true at the moment * Enabled int32 to tests on backends Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I9f8cc6d1c86f832ba46a8d170572f4cfcde9ab17
2020-06-20IVGCVSW-4707 - Add AlignCorners and HalfPixelCenters to ResizeDavid Monahan
* Added AlignCorners and HalfPixelCenters Parameters to Resize * Added Unit Tests Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I83420a9bcb7beec9073d201448f64eb53090e1f1
2020-06-15IVGCVSW-4620 Add Fill Reference ImplementationRyan OShea
* Add Fill Reference Implementation * Refactor FP converter to use static_cast Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I532e2f982981d047690755fac43a0e9cf8b17dcd
2020-06-08IVGCVSW-4860 Add tests to verify QLstm projectionJames Conroy
* Adds int16 output tensor to CpuRef impl to prevent overflow when accumulating output after projection. * Adds two remaining tests to verify QLstm on CpuRef. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I93d7c64c4a9cc1012cb2bc052d598d4279fbd372
2020-06-05IVGCVSW-4904 Refactor CpuRef PAD WorkloadSadik Armagan
* Refactored templated workload creation * Added int8_t unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I018b7f9f20496b5f9d7445901fe0d3dd04199cd0
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-29IVGCVSW-3847 Support INT32 in Gather operatorTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ica217d3e4fbcdef1315554ea5d5c4720124696c3
2020-05-27IVGCVSW-4200 Add CL EXP WorkloadSadik Armagan
IVGCVSW-4203 Add Neon EXP Workload * Added CL EXP operator workload * Added EXP test suite * Enabled EXP tests on ACL and Ref Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I793d31af1b2e3fe86b0bec6d9e5de503c5dab970
2020-05-25IVGCVSW-4863 ADD,SUB,DIV,MUL,MAXIMUM and MINIMUM int32 VTS testTeresa Charlin
skipped in CpuRef Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I1c870ac258e8c3805a95b259cb40731f8e81541e
2020-05-25IVGCVSW-4604 ARGMINMAX float16 VTS test skipped in CpuRefTeresa Charlin
Change-Id: I75cca9804a67f629cddc83671397a84640e9bf0e Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2020-05-02IVGCVSW-4449 Add QLstm ref implementationJames Conroy
* Adds ref implemenation for new HAL 1.3 operator, QLstm. * Adds Layer and CreateWorkload unit tests. * Adds WorkloadData validate for QLstm. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I8a721f07ff06105e6495a1a0561b9503aa8146dc
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