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2021-02-09MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'Sadik Armagan
* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8
2021-01-21IVGCVSW-5616 Don't fuse activation if quantization parameters are differentTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6504e922113aa9e397f53e570ebcf47e1f133945
2020-11-17MLCE-278-IVGCVSW-5530 FusedActivation issuesMike Kelly
* GetOverriddenDataType was returning incorrect quantization data * Optimized CpuAcc and GpuAcc SubGraphs fail validation on debug versions of ArmNN Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ie97935cc2af67bd9aeebc94b63dafa458bd1aa8c
2020-11-17MLCE-278 issue with signed-int8 quantized modelTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I144ebfca524f4cdee9cc82eef3995c6b32bfc40b
2020-11-13IVGCVSW-5328-5329 Fuse Activation CleanupMike Kelly
* Resolved the review items in the main review. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I5da34b74ac204569ea2d210fb5a069beb7d0835b
2020-11-13IVGCVSW-5328-5329 Fuse ActivationMike Kelly
* Added Fused Activation Optimization to both CL and Neon backends. * Added Fused Activation support to all the CL and Neon workloads that support it. * Changed ProfilingTest network to be a Convolution layer followed by an Abs layer rather than an Activation layer. * Added IBackendInternal::OptimizeSubgraphView function that can accept a ModelOptions. * Network will now call OptimizeSubgraphView passing in the ModelOptions. Signed-off-by: Keith Davis <keith.davis@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib536ac3cbafc7d9b35c139ad9a65b7735262cd9d
2020-09-24Add int32 and int64 ArgMax op supportInki Dae
This patch adds int32 and int64 ArgMax op support. Current ARMNN already has ArgMax op but not used, and it doesn't support int64 output type. So this patch adds a new type, Signed64, and also adds ArgMinMax computation function for int64 type support. In default, output tensor type of ArgMax op is int64 in case of tensorflow lite model so this patch makes a proper function - ArgMax op for int64 or int32 - to be called according to parsed output_type value. With this patch, ARMNN supports both types - int64 and int32 - for ArgMinMax op. Changelog v1: - Check if output data type of ArgMinMax op is valid or not. - Use template function to support int32 and int64 types of ArgMinMax function. - Keep using Signed32 as default data type of m_Output_Type. Change-Id: I7a8e7e38dd9e5acc81464571d8b4d51378fc7f14 Signed-off-by: Inki Dae <inki.dae@samsung.com>
2020-09-17IVGCVSW-5300 Remove some boost::numeric_cast from armnn/backendsMatthew Sloyan
* Replaced with armnn/utility/NumericCast.hpp * Some exclusions in reference backend * Excluded as requires float implementation in NumericCast.hpp Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I9e4e9cd502c865452128fa04415fd6f250baa855
2020-08-17IVGCVSW-5229 Add ARMNN_NO_DEPRECATE_WARN_BEGIN to Memory testsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Icd4c84ca6250b6e6d616f64481c5ff60671be9c0
2020-07-29IVGCVSW-5167 Use a generic axis in CL/Neon LogSoftmax and Softmax workloadTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id72d2c2851adcc1dd8f00a6103642b16ebe3a964
2020-07-08IVGCVSW-5005 Fix Deprecated Functions in CL/NEON Resize WorkloadDavid Monahan
* Update CL pin to f3ad9513dd46fca1d6c5e4550286480fdbaba056 IVGCVSW-5005: Fix Deprecated Functions in CL/NEON Resize Workload * Add missing virtual function to NeonIntercepterScheduler * Update CL/Neon Resize Workloads to use ScaleKernelInfo * Update CL/Neon Resize workloads to set correct Sampling Policy for Half Pixels IVGCVSW-4981: Change CL/NEON Softmax axis value * Default value is now 0 Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I8a14c6a64e5a24bc1a66a7d3685cd388c2245702
2020-06-23IVGCVSW-4622 Add NEON FILL WorkloadSadik Armagan
* Added Neon workload for Fill Operator * Enabled Fill operator tests on Neon * NEFill function does not have validate() function yet IsLayerSupported() function return true at the moment * Added INT32 supported type for CpuRef Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I17bf5ec13750f46322a30653e15ba2a514f61f08
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-29IVGCVSW-3846 Add NEON GATHER WorkloadTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I1a66fdad63cef16866d9dfcb8a339647f856e1d4
2020-05-15IVGCVSW-4831 Fix Packet header includes in backendsFinn Williams
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Iedfcf0ef487bd7836b1bc4ba8a0e4337dc4da391
2020-05-13IVGCVSW-4753 Refactor CL Softmax workload generalizing for different datatypeTeresa Charlin
* Change ComputeSoftmaxAclAxis to work with int and uint axis Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ibbfa9ec7e2f0416e6885673212a767419c871cca
2020-04-10IVGCVSW-4483 Remove boost::polymorphic_downcastJan Eilers
* exchange boost::polymorphic_downcast with armnn::PolymorphicDowncast * remove unnecessary includes of boost::polymorphic_downcast Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ie603fb82860fe05fee547dc78073230cc62b2e1f
2020-04-09IVGCVSW-4641 Investigate Hal 1.3 VTS FailuresSadik Armagan
* Add QASYMM8_SIGNED data type support to NeonTensorHandle Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iae34f7d67de83642606ccd8c61a1b72df7f2bb3a
2020-04-06IVGCVSW-4485 Remove Boost assertNarumol Prangnawarat
* Change boost assert to armnn assert * Change include file to armnn assert * Fix ARMNN_ASSERT_MSG issue with multiple conditions * Change BOOST_ASSERT to BOOST_TEST where appropriate * Remove unused include statements Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I5d0fa3a37b7c1c921216de68f0073aa34702c9ff
2020-03-31IVGCVSW-4633 Add conversion of BF16 support to NeonNarumol Prangnawarat
* Add NeonConvertBf16ToFp32Workload * Add NeonConvertFp32ToBf16Workload * Add BFloat16 type support to NeonConstantWorkload and NeonTensorHandle * Add ConvertBf16ToFp32Weight when ConvertBf16ToFp32Layer is added * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Id5b44a203add5e0c98c1ca4e2162115741b56644
2020-03-30IVGCVSW-4603 Support comparison operators in CLTeresa Charlin
* Deprecate ClGreaterWorkload * Add ClComparisonWorkload to encompass all comparison operators Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ida0ed7f59899d75b0fe7de1e7433b1ade018c6f1
2020-03-18IVGCVSW-4446 Add HardSwish EndToEnd testsJan Eilers
* adds convert from armnn HardSwish to Acl HardSwish * adds EndToEnd tests for Ref, Cl and Neon Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: If997dad783ff45d7f061254e7e30bb69d4d4d564
2020-03-02IVGCVSW-4375 Add support for TransposeMike Kelly
* Added TransposeLayer * Added CL, Neon and Ref Workloads * Added Transpose utilities * Added Serializer and Deserializer support * Added Quantizer support Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I04c755ba7cb5b1edf72b3c9f3c0314878032e3c7
2020-02-28IVGCVSW-4439: Adding Elu support to ActivationDavid Monahan
* Added CpuRef implementation * Added Unit Tests * Added Quantizer Test * Enabled Tests for Neon and CL backends on fp32 only * Added to Serializer Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ic23e1797dbc9352b40678c389d7fe2b836b582ea
2020-02-07IVGCVSW-4386 Add ArmNN reference support for QAsymmS8Ryan OShea
* Added Quantization Scheme for QAsymmS8 * Added Unit Tests for QAsymmS8 * Renamed QAsymm8 calls to QAsymmU8 Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Change-Id: I897b4e018ba1d808cc3f8c113f2be2dbad49c8db
2020-01-31IVGCVSW-4388 Update ACL pin to 6a342648ae50beb8457871862f14fc9baef6b74fTeresa Charlin
!android-nn-driver:2671 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifeb6be7812fbb98b37f2a1439bfd5a3215de2a62
2020-01-29IVGCVSW-4149 Enable quantisation multiplier > 1 in all convolutionsRyan OShea
Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Change-Id: I9652844a868ce8e05c0433c051e7079cf203c422
2020-01-24IVGCVSW-4370 Deprecate DataType::QuantizedSymm8PerAxisDerek Lamberti
!android-nn-driver:2622 Change-Id: If99d3eff71ff66ba28af1e5af248299fe04511b9 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2020-01-13Rename quantized data types to remove ambiguity for signed/unsigned payloadsDerek Lamberti
!android-nn-driver:2572 Change-Id: I8fe52ceb09987b3d05c539409510f535165455cc Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-12-31IVGCVSW-4246 Clean build Layers with -WextraDerek Lamberti
Change-Id: I649cd2304fb0040164763d31a12fc77c6c3bed87 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-12-09IVGCVSW-4211 Add Signed 8 bit Quantisation support into the Reference backendFinn Williams
!android-nn-driver:2435 Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I10ecd4a8937725953396805f33a3562a5384c4d4
2019-12-09IVGCVSW-4210 Create a public API for the common backend filesMatteo Martincigh
* Create a public API for the common backend files * Move OutputHandler to armnn internal * Remove unused headers Signed-off-by: Matteo Martincigh <matteo.martincigh@arm.com> Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I3e86d908b021e3561befa9d45158d87d2cbb18c0
2019-11-27IVGCVSW-4148 Extend reporting of quant multiplier > 1 as unsupported on ACL ↵Aron Virginas-Tar
to per-axis case Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I66a8360b6d86e95325dee58927dcbe62ccf6ad58
2019-11-19IVGCVSW-4068 Add Guid to WorkloadNarumol Prangnawarat
* Add Guid to Workload * Remove circular dependency Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Signed-off-by: janeil01 <jan.eilers@arm.com> Change-Id: I15342fa7481c6bdc050e057dce2d74bba07fe2dd
2019-11-19MLCE-144 Cts NNAPI test cases failedMike Kelly
* Fixed numerous CTS/VTS failures related to Quantization Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: If5c20256366e80b6b9bbc46b2a1c410a9b8c48e1
2019-11-08IVGCVSW-4108 Fixed invalid data type exceptionMike Kelly
* Added support for QuantizedSymm8PerAxis to ArmComputeTensorUtils. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ib8662f216bc4b6b54e0099780f73bcf6ef05384b
2019-11-05IVGCVSW-3843 Add support of per-axis quantization to BuildArmComputeTensorInfoAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I0bb0e9da306eee3e19dc9967a6c8bb01da998deb
2019-10-23Fix build failures on RPi 4BJammy Zhou
Signed-off-by: Jammy Zhou <jammy.zhou@gmail.com> Change-Id: I12562c4a9671cd43884e7c0c023ca463a99c3aa2
2019-10-10IVGCVSW-3967 Avg_Pooling2d Fails on CL NHWC FP16Sadik Armagan
* Enable fp_mixed_precision flag for the failing test case Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: If13552165eb6598a84d213b82847b56a8c5f2783
2019-10-01IVGCVSW-3882 Update ACL pinNarumol Prangnawarat
* Update ACL pin to include change of ArgMinMax NEON/CL output type to Signed32 !android-nn-driver:2013 Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I2a0c80e0557f619a213790027efca8b84bf6e58a
2019-08-16IVGCVSW-3620 Fix Hal 1.2 Softmax test failures on GpuAcc and CpuAccColm Donelan
The following NeuralNetworkTests tests were failing on GpuAcc and CpuAcc: GeneratedTests.softmax_v1_2_relaxed GeneratedTests.softmax_v1_2_quant8 GeneratedTests.softmax_v1_2_2 GeneratedTests.softmax_v1_2_relaxed_2 GeneratedTests.softmax_v1_2_quant8_2 The default value for Softmax axis parameter in Android is -1 but is 1 in ACL. Detect and handle this in ArmComputeUtils.ComputeSoftmaxAclAxis. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Ibb0660e4cb0dc6bd4c804c4397fbd61f38acdd9c
2019-08-16IVGCVSW-3639 Add 5d tensor supportMatthew Jackson
* Increased MaxNumOfTensorDimensions and fixed issues related to its use * Fixed issues caused by assuming 5d tensors are invalid * Updated ArmComputeTensorUtils for 5d tensors * Added 5d tensor unit tests for add, mul, stack and reshape (needed by IVGCVSW-3527) Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I5bcd64942d0d04efcc6c5acb240ad4b88e010743
2019-07-25IVGCVSW-3521 CpuAcc V1.2 pad FailuresMike Kelly
* Pad value for QASYMM8 is no longer stored in quantized form. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I048e1d233353c0560ae03a7cc1ed5199295352bc
2019-07-12IVGCVSW-3296 Add CL backend support for ResizeNearestNeighbourAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I7f4c722141837939fd8904c52e75704a15c8a5e3
2019-07-02IVGCVSW-3307 Introduce RefTensorHandleMatthew Bentham
Use it for intermediate tensors on reference backend. Lays the groundwork for memory management in the reference backend. Change-Id: I7d3ee132cac31bde70ae6e1b815f4f0b03d550a6 Signed-off-by: Matthew Bentham <Matthew.Bentham@arm.com>
2019-06-28IVGCVSW-3162 Support CL workload for TransposeConv2DAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I3b021c0828d30298d99ddb211c9aae17fe3636f0
2019-06-24IVGCVSW-3277 Refactor TensorHandle factory APIDerek Lamberti
* Added backend support for multiple types of TensorHandle factories * Refactored the backend API to enable new tensor strategies * Added mechanism to determine memory strategies during optimization * Perform mem-copy only when Direct access is not found * Explicitly deleted the copy-constructor from OutputSlot to prevent accidental local copies that would cause the DisconnectAll to be called by the destructor Change-Id: I7e812c8e5e6c1c20db1c5932749ac70fd93db7f8 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com> Signed-off-by: Matteo Martincigh <matteo.martincigh@arm.com>
2019-06-14IVGCVSW-3278 Cl and Neon TensorHandles inherit from common base interfaceDerek Lamberti
Change-Id: Ia68da09d8f0fb0a04af9cb61062d7edaa5f1b887 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-05-23IVGCVSW-2771 Fix SubTensor error in vgg16 ExecuteNetwork NEONNarumol Prangnawarat
* Add check if Sub-tensors cannot be used, call ACL function * Add computation of SplitAxis from SplitterDescriptor * Add NeonSplitterWorkload functions * Modify IsSplitterSupported to call ACL validate function if sub-tensor cannot be used * Also check if quantization parameters match when using sub-tensors * Add more unit tests for Splitter in TfParser and TfLiteParser Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I31e4c7d055117c83c65b598c4125442173242226
2019-04-10IVGCVSW-2947 Remove boost dependency from include/TypesUtils.hppAron Virginas-Tar
!android-nn-driver:968 Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I03ccb4842b060a9893567542bfcadc180bbc7311
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