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path: root/src/backends/aclCommon/ArmComputeTensorUtils.hpp
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2023-06-07IVGCVSW-7789 Enable dynamic bias in Depthwise Convolution in CpuAccTeresa Charlin
* Dynamic bias are supported by CpuAcc for this layer * Indentation and const modifiers minor changes Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I3b25f14feea55f746c254a832d97e21a1551ca36
2023-04-11IVGCVSW-7507 Pass m_Crops in BatchToSpaceND CpuAcc and GpuAcc workloadsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I902c9187eefe7595271312fdc16273f7aa3d41cd
2023-01-24IVGCVSW-7455 Workaround to allow CLBatchMatMul to parse some 4D modelsMike Kelly
* Added ability to reduce dimension sizes when calling BuildArmComputeTensorInfo or BuildArmComputeTensorShapes, this will attempt to remove leading 1s in order to squeeze the number of dimensions but retain the size. * Changed ClBatchMatMulWorkload to attempt to squeeze the number of dimensions to 3 as the CL Gemm Kernel can only support up to 3 dimensions. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I6b3d0886c5b97fdb686838fc3dc292833ddc4643
2022-12-07IVGCVSW-6853 Rewrite BuildArmComputePermutationVector()Teresa Charlin
* Some pemutation vectors were not converted correctly. * Add Transpose end to end test. * Comments added with an example to clarify the differences betweeen Transpose and Permute Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6c0954ca6ce00ef5f2a6f3625abe6f4fd27b5cdf
2022-12-01IVGCVSW-7272 Add Exception for handling Fp16 infinity valuesKevin May
* Float values which cannot fit in Half are converted as inf/-inf * Add an InvalidArgumentException for infinity displaying the value and data type Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Iaa5671374364c531e29e37fdfe40732b4fdbcfcb
2022-05-12IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete ACLCathal Corbett
* Added backend specific optimization & test for CpuAcc and GpuAcc: PermuteDepthwiseConv2dWeights Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I600476b2e9c557a39818a574c1091c9d650b21b1
2022-04-13IVGCVSW-6174 Add Cl Pooling3d WorkloadRyan OShea
* Add IsSupported for Pooling3d * Add CreateWorkload case for Pooling3d * Create new ClPooling3dWorkload header and source files * Add Pooling3d workload to ClWorkloads.hpp * Add tests for Pooling3d workload * Add Pooling3d build function to ArmComputeTensorUtils Change-Id: Ia270b0fe809a171ed73af14376de8708b346d500 Signed-off-by: Ryan OShea <ryan.oshea3@arm.com>
2022-03-03Revert "Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm ↵Cathal Corbett
fp32/fp16 to Neon"" This reverts commit f87b90e4dbb906436cf205a2a19e199bfe9224ed. Reason for revert: 22.02 release. Change-Id: I1ca5a79a8957908f655a6c4e79eefa24c5aec645
2022-02-23Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 ↵Cathal Corbett
to Neon" This reverts commit b0baff73b1574a198e57d46fcd704cedc43cea16. Reason for revert: cannot update ACL pin until 22.02 release. Change-Id: I049a125ba3b6a9b1cd6514ef9dd14d807773ed00
2022-02-21IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 to NeonCathal Corbett
!ComputeLibrary:7150 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I3de48ffc8d08c95a22705e2b68d069791bddae73
2021-10-27IVGCVSW-6469 Add MirrorPad FrontEnd and Ref SupportMatthew Sloyan
* Added PaddingMode enum to PaddingDescriptor to enable Symmetric and Reflect padding. * Added Symmetric and Reflect Ref implementation. * Added Serializer & Deserializer support. * Added unit tests. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I4bed907b31742b32ccefe5e8ca39a6f1e5bd9dee
2021-10-27IVGCVSW-6170 Add CpuAcc Conv3d WorkloadTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I3a5bfef5a0085d172fd3689e67f25af909ace2ee
2020-09-17IVGCVSW-5300 Remove some boost::numeric_cast from armnn/backendsMatthew Sloyan
* Replaced with armnn/utility/NumericCast.hpp * Some exclusions in reference backend * Excluded as requires float implementation in NumericCast.hpp Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I9e4e9cd502c865452128fa04415fd6f250baa855
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-03-02IVGCVSW-4375 Add support for TransposeMike Kelly
* Added TransposeLayer * Added CL, Neon and Ref Workloads * Added Transpose utilities * Added Serializer and Deserializer support * Added Quantizer support Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I04c755ba7cb5b1edf72b3c9f3c0314878032e3c7
2020-01-29IVGCVSW-4149 Enable quantisation multiplier > 1 in all convolutionsRyan OShea
Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Change-Id: I9652844a868ce8e05c0433c051e7079cf203c422
2020-01-24IVGCVSW-4370 Deprecate DataType::QuantizedSymm8PerAxisDerek Lamberti
!android-nn-driver:2622 Change-Id: If99d3eff71ff66ba28af1e5af248299fe04511b9 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-11-27IVGCVSW-4148 Extend reporting of quant multiplier > 1 as unsupported on ACL ↵Aron Virginas-Tar
to per-axis case Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I66a8360b6d86e95325dee58927dcbe62ccf6ad58
2019-10-23Fix build failures on RPi 4BJammy Zhou
Signed-off-by: Jammy Zhou <jammy.zhou@gmail.com> Change-Id: I12562c4a9671cd43884e7c0c023ca463a99c3aa2
2019-10-10IVGCVSW-3967 Avg_Pooling2d Fails on CL NHWC FP16Sadik Armagan
* Enable fp_mixed_precision flag for the failing test case Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: If13552165eb6598a84d213b82847b56a8c5f2783
2019-08-16IVGCVSW-3639 Add 5d tensor supportMatthew Jackson
* Increased MaxNumOfTensorDimensions and fixed issues related to its use * Fixed issues caused by assuming 5d tensors are invalid * Updated ArmComputeTensorUtils for 5d tensors * Added 5d tensor unit tests for add, mul, stack and reshape (needed by IVGCVSW-3527) Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I5bcd64942d0d04efcc6c5acb240ad4b88e010743
2019-07-25IVGCVSW-3521 CpuAcc V1.2 pad FailuresMike Kelly
* Pad value for QASYMM8 is no longer stored in quantized form. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I048e1d233353c0560ae03a7cc1ed5199295352bc
2019-01-04MLCE-77 Depthwise Convolution with depth multiplier > 1 doesn't workMatteo Martincigh
* Unified ArmNN's weight format to [ M, I, H, W ] for the depthwise convolution * Added conversion utilities to permute/reshape the weights as appropriate when using CL and Neon backends * Updated the reference implementation of the convolution * Updated the relevant unit tests accordingly !android-nn-driver:459 Change-Id: I07d0818efa9d1ca1e5dad82983aac1fe78eadb18
2019-01-02MLCE-82 Add Neon Mean support and unit testsMatthew Bentham
Factor out new BuildArmComputeReductionCoordinates function from CL backend into ArmComputeTensorUtils. Update NEON LayerSupport and WorkloadFactory objects Change-Id: Icc975ec699199bffafbdb207323df509d35e1e04
2018-12-20IVGCVSW-2164 Added ACL implementation of SpaceToBatchNd operation to ArmNNSadik Armagan
!android-nn-driver:428 Change-Id: I42e59ad96d2c80f46b085182855d34b710a74dfe
2018-10-10IVGCVSW-1921: move common Acl code to a separate folderDavid Beck
Change-Id: I400be8e7c0cc5a31eb9d2a7396da145d50d51b6e
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