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2022-05-18IVGCVSW-6147 ConstTensorsAsInput: Optimizer - FusePermuteIntoConstLayerCathal Corbett
* No trailing permute layer after a constant layer * Unit test for optimization Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I0d098f5af41d2c55df7cef1ccfb848093320ddc1
2022-05-18IVGCVSW-6455 Support Const + Dequantize layer and optimize it.Teresa Charlin
* Support Float16 as input to Dequantize layer * Add Optimization to substitute Const+Dequantize layers with Const layer Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I58bb7e3871ca480c7b6fca93c4efb2de84e09e64 Signed-off-by: David <david.monahan@arm.com>
2022-05-16IVGCVSW-6124 ConstTensorsAsInput: Conv2d - FrontEndKeith Davis
* Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Updated Ref. * Fixed resulting Neon / CL tests * Unified optimizers for conv2d ops * Optimizer Fix - Fp32ToBf16 * Partial implementation for ACL backends to fix VTS failures !android-nn-driver:7477 Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I5fb18877f7ee32643e15a9818945356274bb401b
2022-05-12IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete ACLCathal Corbett
* Added backend specific optimization & test for CpuAcc and GpuAcc: PermuteDepthwiseConv2dWeights Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I600476b2e9c557a39818a574c1091c9d650b21b1
2022-05-05IVGCVSW-6127 ConstTensorsAsInput: DepthwiseConvolution2dCathal Corbett
!android-nn-driver:7418 * Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Change NNDriver to new API. * Updated Ref. * Neon and Cl backend partially completed (Backend.cpp files). * Added dynamic or constant input EndToEnd tests. * Added ConstantTensorAsInputMemeberVariableRedirect Optimization. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ib18b6c10a093042e165e25237dc04a4c67ba82da
2022-02-07IVGCVSW-6635 Move MemCopyTestImpl from acl to armnnTestUtils.Colm Donelan
* Move MemCopyTestImpl.hpp from src/backends/aclCommon/test/ to include/armnnTestutils. * Refactor MemCopyTests in aclCommon, cl and Neon. * Introduce RefMemCopyTests to exercise this utility in x86 builds. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I8824f013d3656658ed0a2904bb79384e3af68641
2021-12-15IVGCVSW-6626 Promote backend headers in backendCommon to armnn/backendsColm Donelan
Move the following header files from backendsCommon to armnn/backends. * MemCopyWorkload.hpp * TensorHandle.hpp * Workload.hpp * WorkloadData.hpp * WorkloadFactory.hpp Replace them with forwarding headers and a pragma deprecation message. Resolve the deprecation messages in Arm NN code. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I47f116b30f86e478c9057795bc518c391a8ae514
2021-11-08IVGCVSW-6420: Constant flag in tensor info is not set correctlyCathal Corbett
!android-nn-driver:6532 !armnn-internal-tests:372451 * Made fix to 2 out of 3 ConstTensor() constructors in Tensor.hpp to throw InvalidArgumentException when TensorInfo isConstant parameter is false. * Added new ConstTensor() constructor in Tensor.cpp to accept vector<>.data() using template<typename MemoryType>. * Fixed runtime->GetOutputTensorInfo()/GetInputTensorInfo() methods and called submethods to return TensorInfo& rather than TensorInfo. * Fixed all failing unit tests for CpuRef/CpuAcc/GpuAcc to ensure any ConstTensor created has it's TensorInfo isConstant set to true. * Added unit tests in TensorTest.cpp to ensure ConstTensor constructors throw InvalidArgumentException when TensorInfo isConstat parameter is false. * Added unit test to ensure an empty ConstTensor constructor will set TensorInfo isConatant to true. * Indentation fixes. * Fix to arm_tensor.i to add isConstant parameter to TensorInfo constructor. Added methods IsConstant() and SetConstant(). * Fix to const_tensor.py to throw ValueError when TensorInfo isConstant is set to false when constructing a ConstTensor. * Fixed PyArmnn unit tests to set TensorInfo isConstant to True when ConstTensor is used. * Added unit tests in test_const_tensor.py to ensure ConstTensor constructors throw ValueError when TensorInfo isConstat parameter is false. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I44e440dd0422c366d31bbdbc77ad2b4db0bde148
2021-09-15IVGCVSW-6331 Fixup include directive in RedirectMembersToConstantInputsFrancis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I2503e6995c83316094257318743a756da600bb6c
2021-06-30IVGCVSW-6161 ConstTensorsAsInput: Optimizer - Redirect ConstTensor layer membersMatthew Sloyan
* Optimization that searches for layers with ConstantLayers as inputs. * The layer member variables are then redirected to these ConstantLayers. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I24a2bf0e8575b808343e0bbe3897b344e94796ad
2021-06-16IVGCVSW-5826 Change weights layout for depthwise to [1,H,W,I*M]Jan Eilers
* This change is necessary because tflite uses a [1,H,W,I*M] format and uses the I*M dimension for per axis quantization. Our previous layout [M,I,H,W] can't handle the correlating quantization scales. * Updates Onnx-, TfLiteParser and TfliteDelegate * Updates the CpuRef, CpuAcc and GpuAcc backends * Adjusts unit tests * Adds test to ensure models with old layout can still be read and executed * Adds conversion function to previous layout [1,H,W,I*M] --> [M,I,H,W] which can be used by backend developers !android-nn-driver:5553 Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ifef23368b8c3702cf315a5838d214f7dc13c0152
2021-05-25IVGCVSW-3649 Add Prelu with different alpha dimension test to TfLiteParserNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I982ecd66ea3ed4d88934cd8254832eecb4a7adb4
2021-05-24IVGCVSW-6069 Fold PAD into Depthwise ConvolutionTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib01629256309cfe17f341909d5b9bbbb09361422
2021-05-06IVGCVSW-5815 Generalise ConstCpuTensorHandleJames Conroy
* Generalises ConstCpuTensorHandle and inherited classes by removing 'Cpu' from aliases. * New renamed classes: ConstTensorHandle, TensorHandle, ScopedTensorHandle, PassthroughTensorHandle, ConstPassthroughTensorHandle. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I1824e0e134202735fb77051f20a7252f161dfe16
2021-04-29IVGCVSW-5890 Prevent modification to const layers with multiple connectionsColm Donelan
* In AddBroadcastReshapeLayerImpl check if a constant layer has other connections before modifying its output tensor shape. * In ElementWiseBaseLayer replace an ARMNN_ASSERT with a proper error message. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Id3f3796c260eede61f076660505257a8b65d93fc
2021-04-21Fold PAD into Pooling2d if possibleDiego Lopez Recas
Some models would add a PAD layer before a pooling when they can't express their padding configuration as SAME or VALID. ArmNN can potentially merge the two merge the two because pooling layers are described with explicit padding. The merge is possible if the extra padding is neutral in the combined pooling operation. A merged operation can only fuse paddings in the dimensions that accept explicit padding in a pooling operation, i.e. the spatial dimensions. Signed-off-by: Diego Lopez Recas <diego.lopez.recas@gmail.com> Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Icd54718dcd9e797c923456b7fa6e0213e288e668
2021-04-07Fix graph copy memory spikeFinn Williams
* Change layer storage of ConstTensors to std::shared_ptr<ConstCpuTensorHandle> * Change clone to share ConstTensor rather than copy * Remove uses of non-const GetTensor() call * Reduce scope of non-optimized network in ExeNet, so memory can be released after use Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Ibb2c7309d12411d21405bd6024c76bcdf5404545
2021-03-23Revert "Fold PAD into Pooling2d"Jim Flynn
This reverts commit 51ce7d487c761358de105f82ff90553570aedac0. Reason for revert: https://jira.arm.com/browse/IVGCVSW-5798 LargeGraph_TENSOR_FLOAT32 CTS tests failures Change-Id: Ib031a47f605340b2202ecf074ce96a8b54c51075
2021-03-22Fold PAD into Pooling2dDiego Lopez Recas
Some models would add a PAD layer before a pooling when they can't express their padding configuration as SAME or VALID. Arm NN can merge the two because pooling layers are described with explicit padding. Signed-off-by: Diego Lopez Recas <diego.lopez.recas@gmail.com> Change-Id: Id048186db6a005e0257bfbc1406c3b0dab2cdd58
2021-03-16IVGCVSW-5754 Change the behaviour of the AddBroadcastReshapeLayer ↵Finn Williams
Optimisation when the input is a const tensor Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I8b1357bdefc45880d064d7e448af364ac8644c0d
2021-01-25IVGCVSW-5619 Add OptimizerOptions and NetworkProperties to ArmNN DelegateNarumol Prangnawarat
* Add OptimizerOptions, NetworkProperties, DebugCallbackFunction to DelegateOptions * Enable OptimizerOptions when the network is being optimized * Enable NetworkProperties when loading network * Enable DebugCallbackFunction * Add error message when loading network * Log warning instead of error when operator is not supported but could fallback to another backend * Improve uint16_t CompareData * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I353035afb442774bfeb1c62570a90755c2ceaf38
2020-11-17IVGCVSW-5530 'Cannot run SSD Mobilenet f16/uint8 on CpuRef via ExecuteNetwork'Sadik Armagan
* Added FP16 DataType support to DetectionPostProcess * For DetectionPostProcess layer output is always Float32 regardless of input type Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I21f63dd08f0863e9a98e105b3009bab3da1ab0c3
2020-11-08IVGCVSW-5315 Create FuseBatchNorm classMike Kelly
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Id0625c58dbeea79874bf986b70d136ed9390bf83
2020-10-29IVGCVSW-5314 Create OptimizeForExclusiveConnectionTeresa Charlin
* FuseBatchNorm class has been added to facilitate testing * Only Convolution2D FP32 being fused Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I049c4770946ddca21b08516d4c9f4d0d22bf9b45
2020-09-15IVGCVSW-5305 AddBroadcastReshapeLayer as optimizerNarumol Prangnawarat
* Remove AddBroadcastReshapeLayer from TfLiteParser * Add AddBroadcastReshapeLayer as optimizer * AddBroadcastReshapeLayer optimizer unit tests * Load-scope dynamic tensor broadcasting unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I3549e85b71b41cbd4d96c0f1ece7887acbca76d1
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-19IVGCVSW-4669 Set destination tensorInfo in MoveAllConnections()Finn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I3563209dcb3db1b40cf2db3855adc631b5e323be
2020-04-10IVGCVSW-4483 Remove boost::polymorphic_downcastJan Eilers
* exchange boost::polymorphic_downcast with armnn::PolymorphicDowncast * remove unnecessary includes of boost::polymorphic_downcast Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ie603fb82860fe05fee547dc78073230cc62b2e1f
2020-04-06IVGCVSW-4485 Remove Boost assertNarumol Prangnawarat
* Change boost assert to armnn assert * Change include file to armnn assert * Fix ARMNN_ASSERT_MSG issue with multiple conditions * Change BOOST_ASSERT to BOOST_TEST where appropriate * Remove unused include statements Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I5d0fa3a37b7c1c921216de68f0073aa34702c9ff
2020-03-26IVGCVSW-4597 Modify BF16 optimizer to Convert only inputs and weights ofNarumol Prangnawarat
Convolution2d and FullyConnected layers * Add InsertConvertFp32ToBf16LayersBefore * Add ConvertWeight to ConvertFp32NetworkToBf16Impl for Conv2d and FullyConnected * Allow different input and output when input is BF16 and output is FP32 Conv2d and FullyConnected layers * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ic8f92ff28edcae08a72a3114a28f50c4619f919b
2020-03-20IVGCVSW-4520 Implement BFloat16 OptimizerNarumol Prangnawarat
* Add ReduceFp32ToBf16 to OptimizerOptions * Add ConvertFp32NetworkToBf16 * Add utility functions to insert conversion layers * Add constant conversion BF16 <-> FP32 * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Iaff77e20c721400b052cb37eb9ef6fe16d7abaff
2020-03-10IVGCVSW-4482 Remove boost::ignore_unusedJan Eilers
!referencetests:229377 Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ia9b360b4a057fe7bbce5b268092627c09a0dba82
2020-03-03IVGCVSW-4375 Add support for Transpose to optimizationsMike Kelly
* Changed some existing Permutation specific optimizations to also support Transpose * Added MoveTransposeUp optimization * Added TransposeAsReshape optimization * Added tests for Transpose optimizations * Added missing layer tests for Transpose Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I20d099b284861402ae94aaa5dbf34907327a485f
2019-12-30IVGCVSW-4246 Clean build optimizations with -WextraDerek Lamberti
Change-Id: I2e0884c66855071eb3aa72b86de06c6ed6389d50 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-11-29MLCE-143 Fixed driver crash during CTS testsMike Kelly
* Only apply the Optimization when the base ReshapeLayer is connected to the child ReshapeLayer and no other Layer. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Iccd676d657f9e7c829813f1bec9c82db8745d069
2019-11-29IVGCVSW-4209 Create a public API for the ArmNN UtilsMatteo Martincigh
* Moved the relevant armnnUtils headers to the new location: include/armnnUtils * Update the header usage throughout the source code !android-nn-driver:2387 Signed-off-by: Matteo Martincigh <matteo.martincigh@arm.com> Change-Id: I2ba15cebcacafad2b5a1a7b9c3312ffc585e09d6
2019-11-15IVGCVSW-4119 Fix FP16 to FP32 fallback mechanism in optimizer to work with ↵Aron Virginas-Tar
Dequantize * Check for output data type as well as input data type when determining whether we should attempt to fall back to FP32 if FP16 is not supported * Override output type for Dequantize in IsLayerSupported() instead of input type * Updated original input type from FP16 to FP32 in InsertConvertFp32ToFp16LayersAfter() Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Ic6477fd17cea5a91bd8bf9ae0cf836520897d5b7
2019-09-27NNXSW-1826 Add an optimization step which combines Permute and BatchToSpace ↵Rob Hughes
into DepthToSpace This is only possible in some limited cases, but removes an extra layer from the graph and so should improve performance in all cases. Change-Id: I7b3e6ba5dacb4fdb816ad270edaecda1436ab4cf Signed-off-by: Rob Hughes <robert.hughes@arm.com>
2019-09-24NNXSW-1826 OptimizeConsecutiveReshapes: remove unnecessary call to ↵Rob Hughes
MoveAllConnections This is called at a time when newReshape has nothing connected to its output slot (as it has just been created) and so is a no-op. The code comment indicated that the intention was to connect the newReshape to its *input*, but that has already been done in the InsertNewLayer() call above, so the comment was incorrect. There is a unit test covering this case ("OptimizeConsecutiveReshapesTest") Change-Id: I933d5d1c6eb32f5a8269fb5d7c809cd7c89680d1 Signed-off-by: Rob Hughes <robert.hughes@arm.com>
2019-05-13IVGCVSW-3058 Segmentation fault running Resnetv2.50 tfite int8 modelMatteo Martincigh
* The execution crashed because the weights of a convolution were null during the network execution * Copied the weights and bias when folding a pad layer into a convolution Change-Id: I3ae72143d04cac90d4f878cdf3b1a08b2f2a5c90 Signed-off-by: Matteo Martincigh <matteo.martincigh@arm.com>
2019-04-19IVGCVSW-2925: Combine Pad with Convolution2d in the OptimizerNina Drozd
* Added new optimization for folding pad layer into convolution2d layer following it * Added new test in OptimizerTests.cpp * Added new optimization into All optimizations * Added call to new optimization in Optimize in Network.cpp * Updated CMakeLists.txt Signed-off-by: Nina Drozd <nina.drozd@arm.com> Change-Id: I682e07c71bbd42c49c02dda30a848a9ab2b16e7e
2018-12-11IVGCVSW-1434 Add debug mode to Optimizerkeidav01
* Modified optimizer to support debug mode via DebugLayer Change-Id: Ic8f313778e55540c182cf99876c44a0823be04c6
2018-11-02IVGCVSW-1946: Remove armnn/src from the include pathsAron Virginas-Tar
Change-Id: I663a0a0fccb43ee960ec070121a59df9db0bb04e
2018-10-10IVGCVSW-1913: Fix for ValidationTest.concat_float_3_relaxedarovir01
* Added RefPermuteFloat16Workload to serve as a fallback when CL does not support the required permute configuration for FP16 * Move Half.hpp to armnnUtils as the utils library should not be including private header files from the armnn library Change-Id: Ibf0f698451e8406f7ed7cce470dab60b6d16361d
2018-10-10IVGCVSW-1900 : CL backend folder structureDavid Beck
* moving backends/ClWorkloads to backends/cl * and moving pure Cl workload related code to backends/cl/workloads Change-Id: I019a3c6b4da5e7a23074bf03fb057e63199ad129
2018-09-17IVGCVSW-1807 : change license text in file headersDavid Beck
All changes are the same: // // Copyright © 2017 ARM Ltd. All rights reserved. -// See LICENSE file in the project root for full license information. +// SPDX-License-Identifier: MIT // Change-Id: I37eae011411133663ca9d2b059714d92f8bf8e24
2018-08-31Release 18.08telsoa01
2018-03-29Release 18.03surmeh01
2018-03-09Release 18.02telsoa01
Change-Id: Id3c11dc5ee94ef664374a988fcc6901e9a232fa6
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