armnn.git -

Age	Commit message (Collapse)	Author
2019-04-16	IVGCVSW-2957 MergerLayer subtensor optimization now backend agnostic	Derek Lamberti
	+ Update clframework pin + Cl and Neon Merger workloads updated to use MemoryLayout agnostic API + Workloads only use sub-tensor optimization if ALL input tensors are sub-tensors + Refactor LayerSupportCommon code to be a bit more succinct Change-Id: Ib61ad4ccbd767e924dff07e61022e0cda4069828 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-02-22	IVGCVSW-2749 Throw exception in TensorShape when requested index >= number ↵	Aron Virginas-Tar
	of dimensions Change-Id: I3589b1e901b0f81f6bb17848046a22829f91bb9e Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com>
2018-12-07	IVGCVSW-2268 Remove the input swizzling from ParseConcat	Matteo Martincigh
	* Removed the input swizzling when the concatenation dimension is 3 in ParseConcat in the TF parser * No longer using the helper ProcessConcatInputTensorInfo, where the input was being swizzled if the concatenation dimension was 3 * Added a new convenience constuctor to TensorShape that initializes a shape to all zeros given only the number of dimensions Change-Id: I82a207e41bddc5fea21a0b5a38eafa24ad75d1c2
2018-09-17	IVGCVSW-1807 : change license text in file headers	David Beck
	All changes are the same: // // Copyright © 2017 ARM Ltd. All rights reserved. -// See LICENSE file in the project root for full license information. +// SPDX-License-Identifier: MIT // Change-Id: I37eae011411133663ca9d2b059714d92f8bf8e24
2018-08-31	Release 18.08	telsoa01

2018-03-09	Release 18.02	telsoa01
	Change-Id: Id3c11dc5ee94ef664374a988fcc6901e9a232fa6