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2020-11-17IVGCVSW-5465 ExecuteNetworkTestsDynamicBackends Bug FixKeith Davis
* When invalid backend specified an ARMNNLOG should be invoked to fail more gracefully Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Iec34fbc03dbeeb66836b0d5e1dd381d021a379b1
2020-11-17IVGCVSW-5463 Change cmake version for delegate to 3.7Jan Eilers
Signed-off-by: Jan Eilers <jan.eilers@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Idb3f9018a22d0f63c0f993fdfd282a1195454ac9
2020-11-17Added SECURITY.md fileMike Kelly
* New file contains the security policy, vulnerability reporting procedure and a PGP key that can be used to create secure vulnerability reports. * Removed Security section from README.md Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ifdffdf81a7d2033a4fa323f081a7336504d67971
2020-11-17IVGCVSW-5311 Debian Packaging - Host packages in public PPAFrancis Murtagh
* Add guide to github README.md Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I23df585ee24e90629f821af0c780ad40d8c20f97
2020-11-17MLCE-278 issue with signed-int8 quantized modelTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I144ebfca524f4cdee9cc82eef3995c6b32bfc40b
2020-11-16Update ACL pin to 17b7102b30e0159263d06d3a0816cd2998a13456Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I4e664e51e9f03f1a19830fde199a9c158dfaaa3d
2020-11-16IVGCVSW-5508 Activate compiler warnings in ArmNN TfLite DelegateFinn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I1a8e2aa618ff693c61010e6150f3ca41b8ab1201
2020-11-16Update ACL pin to 61ffda4839d6fe8cc165faae0ec7c9be1d528194Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ib738b3e333540a683c452a927ab155e0775473e7
2020-11-16IVGCVSW-5385 TfLiteDelegate: Implement the Transpose operatorJames Ward
Signed-off-by: James Ward <james.ward@arm.com> Change-Id: Iea3d7ecccb82d85ec2d2c5cfdcdaf692236a60aa
2020-11-16IVGCVSW-5338 TfLiteDelegate: Implement the Convolution operatorsSadik Armagan
* Add Convolution, DepthwiseConvolution and TransposeConvolution Signed-off-by: Kevin May <kevin.may@arm.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I797e42844dfee0cc80beb64eabc3111b96320daf
2020-11-13IVGCVSW-5189 Fix error running EfficientNet-Lite on GpuAccNarumol Prangnawarat
* Correct datatype of QAsymmS8 Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Id4987b91e06d87735254d3cdd5c9adbe11cc8870
2020-11-13IVGCVSW-5328-5329 Fuse Activation CleanupMike Kelly
* Resolved the review items in the main review. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I5da34b74ac204569ea2d210fb5a069beb7d0835b
2020-11-13Wrap FindBoost in if(BUILD_UNIT_TESTS) so that it can be excluded entirelyMatthew Bentham
Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: Iabe1b10e53d393a19e681156c001d6a2e9eb835e
2020-11-13IVGCVSW-5346 Update Major, Minor release versionsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I10bae415c175f4f35f32829fc48473c2ca5fa1d8
2020-11-13IVGCVSW-5328-5329 Fuse ActivationMike Kelly
* Added Fused Activation Optimization to both CL and Neon backends. * Added Fused Activation support to all the CL and Neon workloads that support it. * Changed ProfilingTest network to be a Convolution layer followed by an Abs layer rather than an Activation layer. * Added IBackendInternal::OptimizeSubgraphView function that can accept a ModelOptions. * Network will now call OptimizeSubgraphView passing in the ModelOptions. Signed-off-by: Keith Davis <keith.davis@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib536ac3cbafc7d9b35c139ad9a65b7735262cd9d
2020-11-13IVGCVSW-5495 Fix validation for per-channel quantJames Conroy
* Now enter if block if bias OR weights have multiple quantization scales. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I5eba0ceac9b347d0e3467e86d72d587b749b9521
2020-11-12Update ACL pin to d7341fb9e3b24b904edf7ac9d83e1e063bc77765Teresa Charlin
* Use NEConvolutionLayer Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ieb81fafaf34a63be8daf297ebe1bb0e4079daf4e
2020-11-12IVGCVSW-5396 TfLiteDelegate: Implement the Resize operatorsJan Eilers
* Added resize biliniear and nearest neighbour operator support to the tflite delegate Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Id0113d6b865ea282c6f4de55e8419a6244a35f0e
2020-11-12Update ACL pin to 5f2fb59054aee2ec190d72accdb45f852caf4b87Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I573687e7b81cbbf56f6f578d12c59e3ed5cda2d8
2020-11-12IVGCVSW-5504 'TfLiteDelegate: Introduce FP16 and BackendOptions'Sadik Armagan
* Added BackendOptions creations of armnn_delegate * Included armnn/third-party the armnn_delegate unit tests * Updated the CreateConstTensor function Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8e2099a465766b905bff701413307e5850b68e42
2020-11-11IVGCVSW-5387 TfLiteDelegate: Implement the Pooling operatorsNarumol Prangnawarat
* Add support for AveragePool2d and L2Pool2d operators * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ida3c2e80120bce2991035f143e9eb5b9480b0e4b
2020-11-11IVGCVSW-5507 ExecuteNetwork fixJan Eilers
* Allow multiple backends to be defined seperately like " --compute CpuAcc --compute CpuRef " Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ic2a827f6e3463a7413c98a7eefacef8864c1e87b
2020-11-11Update ACL pin to 087ee3d521c1137b0bc611579eb1b94cc7813fb2Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I35db3c917c5651b100f61c3dca35cee2245dd676
2020-11-10IVGCVSW-5389 'TfLiteDelegate: Implement the FullyConnected operator'Sadik Armagan
* Added FullyConnected operator support to delegate Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iae9c0980a4bfd6aa4d90f107f329dfa782baeefe
2020-11-10IVGCVSW-5387 TfLiteDelegate: Implement the Pooling operatorsNarumol Prangnawarat
* Implement MaxPool2d operators * Add QAsymmS8 to armnn delegate * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I1815ade6ccda3e9331bd3a68e164be0f6947e9df
2020-11-10IVGCVSW-5398 TfLiteDelegate: Implement the Quantization operatorsMatthew Sloyan
* Enabled quantization operators DEQUANTIZE and QUANTIZE. * Implemented unit tests for quantization operators. * Added utils function for checking if affine quantization. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I84b5c75bda629d9234f5ed198b04f527705a54aa
2020-11-10IVGCVSW-5380 'TfLiteDelegate: Implement the Comparison operators'Sadik Armagan
* Implemented Comparison Operators * Added unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Icdc0f7c6a286a8364a2770b26d15e8958291dc2b
2020-11-10IVGCVSW-5379 'TfLiteDelegate: Implement the ElementWiseBinary operators'Sadik Armagan
* Enabled elementwise binary operators DIV, MAXIMUM, MINIMUM, MUL, SUB * Implemented unit tests for elementwise binary operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I196998d53201a6e8888bb203eb640530b8feeac9
2020-11-10Update ACL pin to 2cb05d9ee91880179ad2537cbf66229c7c2a2356Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I4672cd8827f6c03243213a5f1ce45e8f1cd3044a
2020-11-09IVGCVSW-5091 Add Logical ops frontend and ref implJames Conroy
* Add frontend and reference implementation for logical ops NOT, AND, OR. * Unary NOT uses existing ElementwiseUnary layer and ElementwiseUnary descriptor. * Binary AND/OR uses new layer LogicalBinary and new LogicalBinary descriptor. * Add serialization/deserializion support and add missing ElementwiseUnary deserializer code. * Add additional Boolean decoder in BaseIterator.hpp. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Id343b01174053a166de1b98b6175e04a5065f720
2020-11-09IVGCVSW-5462 Link fmt staticallyJan Eilers
* Fmt didn't get installed properly. Each component of an interface library needs to be installed separately. * Changed fmt to be a static library Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ic69bc9536ee01eed7b434b1ff53150581ba60e00
2020-11-09Update ACL pin to bef7fa27b0d231a8649952f60808132d109b6345Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I842bb25a5c4dfda7e195e71af41e829bc6c5ea21
2020-11-09IVGCVSW-5327 Add to Layer a binary blob to host the activation layer infoKeith Davis
Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I0a07dea96a86849701ba387dbea148909a6d729b
2020-11-08IVGCVSW-5315 Create FuseBatchNorm classMike Kelly
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Id0625c58dbeea79874bf986b70d136ed9390bf83
2020-11-08COMPMID-3639: (3RDPARTY_UPDATE) Move CL kernels to srcFrancis Murtagh
* Change file Armnn GlobalConfig.cmake uses to find ARMCOMPUTE_INCLUDE * Original file has been moved and no longer visible Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I91c1376124dad2b2db764f83c421a1cc110e5dd1
2020-11-05Remove URL_HASH check for x264 libÉanna Ó Catháin
Change-Id: I45a98a1f3108397c31389901284967e1611d61f8 Signed-off-by: Éanna Ó Catháin <eanna.ocathain@arm.com>
2020-11-05Update ACL pin to 770dfeb04b6fd89afde2005bd46caa6ff0858f3eNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I6a0b1c2fe3f98f2bce31296f732ddd914522a9c0
2020-11-04Update ACL pin to ca6068594bcabcc392f30c8ff3188b03f4a35407Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6f71845179e22cc7b05e3d1e3adddea998962770
2020-11-02IVGCVSW-5476 Fix Fuse_batchNorm_into_Conv2D_Float32_TestTeresa Charlin
* failing with no backends provided Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I55ebfc52268ad667e495831c64977338d003db99
2020-10-30Print out more information about the graphAyan Halder
Besides, the layer name, type and backend, it is useful to print the count of input/output tensors. Also, we could print the tensor dimensions. Signed-off-by: Ayan Halder <ayan.halder@arm.com> Change-Id: I91ac09ae1d594e13f01e1db60dc531b16ae87dde
2020-10-30IVGCVSW-5322 Fix segfault between Neon and Cl layersNarumol Prangnawarat
* Fallback to memory copy if memory import is not supported * Remove direct compatibility between Neon and Cl Tensors * Unit tests fallback from Neon to Cl and Cl to Neon Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Iec00a77423fb23b37a6b1aefee1b2ec4d649efca
2020-10-30IVGCVSW-5265 Removing more Boost references from test executables.Colm Donelan
* Removed unused includes from InferenceModel.hpp. * Replaced use of boost multi-array with vectors in YoloInferenceTest. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Ieadf3471ed170b09859187c83616c8e249f94543
2020-10-30IVGCVSW-5267 Remove boost from core android-nn-driverJames Ward
Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I19088511be05087f979aa285242dd18f093fc5da
2020-10-30IVGCVSW-5266 Remove Boost from standalone dynamic backendJames Ward
Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I11e02826dd155bc722d6659d9b7e3053cad45b7f
2020-10-29IVGCVSW-5468 Rewrite QuantizationDataSet.cpp to avoid use of CsvReaderJames Ward
* Remove armnnUtils/CsvReader and usage * Remove armnn/CsvReaderTest and usage * Replace functionality in QuantizationDataSet.cpp Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I7213904482afa93ae6d607aa5e69117c8c34ea81
2020-10-29IVGCVSW-5379 'TfLiteDelegate: Implement the ElementWiseBinary operators'Sadik Armagan
* Implemented ADD operator * Implemented FP32 unit tests for ADD operator Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Id7238749308855bd2b2118f4b6e60e765815c38f
2020-10-29IVGCVSW-5267 Remove boost from core android-nn-driverJames Ward
* WIP !armnn:4246 Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I1b379b9e7f4397ca9b9189e423042469af382c09
2020-10-29IVGCVSW-5265 Remove boost from core ArmNN CMakeColm Donelan
* Remove all but Boost_UNIT_TEST_FRAMEWORK_LIBRARY from ArmNN Cmake files. * Remove references to boost::fpc from old test applications. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Ibb1261dee4b971d1788d2805528aa800a8b883ce
2020-10-29IVGCVSW-5314 Create OptimizeForExclusiveConnectionTeresa Charlin
* FuseBatchNorm class has been added to facilitate testing * Only Convolution2D FP32 being fused Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I049c4770946ddca21b08516d4c9f4d0d22bf9b45
2020-10-29Update ACL pin to 5a4284dc7d98a382d0fa492b64fabe430d5afdc6Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ife58d18880bc561bede5cd432befb632fe9dc9c9
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