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2021-04-12Update ACL pin to 99b1a1cc1bdeaec08d2a8fb5ac5d104502e05570Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ife010f2eebace4efbf90c2469cea88175b522a76
2021-04-12Documentation - Add "How to get involved" section to README.mdFrancis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I5919c9b93f335e09e542c7ecfbcba637f64df3b8
2021-04-09IVGCVSW-5804 TfLiteParser fails to correctly parse ArgMinMaxMatthew Sloyan
* Fix for GitHub#523. * Updated ParseArgMinMax function to read correct axis data. * Improved validation in ParseArgMinMax function. * Added ARG_MIN support to TfLiteParser. * Added ArgMinMax unit tests for TfLiteParser. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ib4ce1a7c66e210c47859a130c4896aac958f2654
2021-04-09MLCE-328 Serializer/Deserializer does not support Signed64Mike Kelly
* Added support for Signed64 to flatbuffer's schema & updated source tree * Added support for Signed64 to TFLite Delegate * Added support for Signed64 to Serializer * Added support for Signed64 to Deserializer * Added unit test for ArgMinMax to Deserializer * Deprecated m_Output_Type from the ArgMinMaxDescriptor: the output type is solely determined by the DataType of the output Tensor * Fixed issue where RefArgMinMaxWorkload could output data using the wrong DataType * Added Signed64 to RefLayerSupport::IsArgMinMaxSupported as a supported type Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ib622c052a1f8aa3e658262f8bde5a6881a8cbe10
2021-04-09IVGCVSW-5803 Delegate Unit Tests Failure on Android: Normalization & SoftmaxKeith Davis
Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I2873f8563cc11da550d460b04e5175372489a564
2021-04-09Update ACL pin to 3b5981ce898569aafa98abdf220c73f1a80685b9Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ie82f312cd09ece61c3e5c11b653b9a7511f23620
2021-04-08IVGCVSW-5823 Refactor Async Network APIMike Kelly
* Moved IAsyncNetwork into IRuntime. * All LoadedNetworks can be executed Asynchronously. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ibbc901ab9110dc2f881425b75489bccf9ad54169
2021-04-08IVGCVSW-5793 Add default ExecuteAsync implementation to WorkloadFinn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: If2069b4d274286e654ac2bceb52d147f9ee3a7a9
2021-04-07IVGCVSW-5768 Output layer bindings are ignoring outputSlotIndex.Colm Donelan
In the bug there were 4 outputs from the final layer. The de-serialized layer bindings were incorrectly assigning the tensor info of one output to all 4 outputs. The solution is to use outputSlotIndex. One other minor fix: The debug text referred to an Input when dealing with an output. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: I6c68b781a450ae4a5cf1d0e8671bb96ff01862b2
2021-04-07Fix graph copy memory spikeFinn Williams
* Change layer storage of ConstTensors to std::shared_ptr<ConstCpuTensorHandle> * Change clone to share ConstTensor rather than copy * Remove uses of non-const GetTensor() call * Reduce scope of non-optimized network in ExeNet, so memory can be released after use Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Ibb2c7309d12411d21405bd6024c76bcdf5404545
2021-04-07Update ACL pin to c5b1beec99d2be7ff3babbc6345b1baa81f29eb7Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ic3efd8106be43ff2c1d250238d162e51e3a86a57
2021-04-07IVGCVSW-5422 Add per-channel quantization tests to depthwiseJan Eilers
Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ie51ce20540e5e7a704ce2b4be4e8cf64f91ea990
2021-04-02IVGCVSW-5783 'Add AsyncExecution Capability'Sadik Armagan
* Added AsyncExecution to the BackendCapability enum class. * Logged a warning if backends do not support AsyncExecution capability if AsyncNetwork is created. Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I49f8467297f4b6b8e414cb6a3638a7d3f1bb886a
2021-04-01IVGCVSW-5651 'Regression in CLConvolution2dWorkload'Sadik Armagan
* Enable GPU profiling on ExecuteNetwork Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I57bb4eeb45674e5218fce7e67b9bddf16ba0894d
2021-04-01Update ACL pin to 33f41fabd30fb444aaa0cf3e65b61794d498d151Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: If0921a9f4d5c9a61dac30a43650fbb5a875b8ce7
2021-03-30Update ACL pin to 2788609b8a10306e9eae47543b39812a7b075aaaNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I11c1a61a6ff7a7252f086b61a9fc14ec48dd9efc
2021-03-30IVGCVSW-5799 'Create Pimpl Idiom for Async prototype'Sadik Armagan
* Implemented Pimpl Idiom for IAsyncNetwork Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ic7311880563568b014a27f6347f8d41f2ad96df6
2021-03-30Update x86_64 DockerFile for armnnKeith Mok
Fix break for DockerFile Signed-off-by: Keith Mok <ek9852@gmail.com> Change-Id: I0c0b10fa212583b8861301fb9e1e926237b7867d
2021-03-29IVGCVSW-5676 Fixing build failure in backends jenkins job.Colm Donelan
* Adding ref backend "ifdef" around ref test cases in NeonLayerTests_NDK_Bug.cpp * Removing unnecessary includes from NeonLayerTests_NDK_Bug.cpp. * Removing unnecessary include from NeonLayerTests.cpp * Breaking up Backends_Capability_Test into one per backend to allow for conditional compilation. * Remove unnecessary printout in src/backends/neon/test/CMakeLists.txt Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: I9a36cd197e684ed55af244e5c998ee67bb8da88c
2021-03-29Update ACL pin to 1e3ab4264fb0455abe8a3903abab40c59b9be91eNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I096f8f6f3c7352fdfa11eca5423c461082a1f163
2021-03-29IVGCVSW-5790 Merge async prototypeMike Kelly
* Added thread safe execution mechanism for armnn * Removed duplicate function bool Compare(T a, T b, float tolerance) * Added StridedSliceAsyncEndToEndTest * Fixed memory leak Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I2d367fc77ee7c01b8953138543e76af5e691211f
2021-03-26Correct TuningLevel enumeration valuesInki Dae
According to the header description - include/armnn/IRuntime.hpp, Each level should have below value. ----------------------------------------------------------------------------------------------------- "TuningLevel" : int [0..3] (0=UseOnly(default) | 1=RapidTuning | 2=NormalTuning | 3=ExhaustiveTuning) ----------------------------------------------------------------------------------------------------- And also src/backends/cl/ClBackendContext.cpp uses below enumeration values internally for the tuning level, ---------------------- enum class TuningLevel { None, Rapid, Normal, Exhaustive }; ---------------------- So this patch corrects TuningLevel enumeration values - which is exposed to user - to be consistent with ones internally used. Change-Id: I9a8aeea0115579bfd16cbe01f39183b96329cdfd Signed-off-by: Inki Dae <inki.dae@samsung.com>
2021-03-25IVGCVSW-5741 Update FullyConnected in TfLiteParser to support NonConstWeightsFinn Williams
!armnn:5180 * Remove unnecessary memcopy for non permeuted const tensors Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Idc3ce2ac001e7d6be61819279de486f093730383
2021-03-25IVGCVSW-5676 Eliminating some Neon unit tests for debug builds.Colm Donelan
* Creating a new NeonLayerTests_NDK_Bug test class. * Moving a subset of tests effected by an NDK bug from NeonLayerTests into NeonLayerTests_NDK_Bug. * Excluding NeonLayerTests_NDK_Bug from the build if it's an Android debug build and NDK is less than r21. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Icb16d8bbb784fb0357deef281d7aa713e11af8ac
2021-03-25IVGCVSW-5736 and IVGCVSW-5743 'NonConstWeights: Update front-end and ↵Sadik Armagan
TfLiteDelegate support for FullyConnected Operator' * Added front-end support for non-const weights for FULLY_CONNECTED operator * Added FULLY_CONNECTED end-to-end test * Updated FULLY_CONNECTED operator support in TfLite Arm NN Delegate for non-const weights * Updated the version numbers Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iffa5b9aa9297aca4c02d923cce4636c88ac21faa
2021-03-24Fix YoloV3 test program incorrect use of absKeith Mok
abs is int type, use fabsf instead for float type Signed-off-by: Keith Mok <ek9852@gmail.com> Change-Id: I157d471da25d66cbe39fa9809ff9ee536d4e95a1
2021-03-23Update ACL pin to 226169fef38e2361f6b503570645c802c513112dNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I482d3d6aebc409478c524811ebd41fc1a6c37e5a
2021-03-23Revert "Fold PAD into Pooling2d"Jim Flynn
This reverts commit 51ce7d487c761358de105f82ff90553570aedac0. Reason for revert: https://jira.arm.com/browse/IVGCVSW-5798 LargeGraph_TENSOR_FLOAT32 CTS tests failures Change-Id: Ib031a47f605340b2202ecf074ce96a8b54c51075
2021-03-23IVGCVSW-5724 Add import tensor handling as ClImportTensorHandleFactory.Colm Donelan
* Add new ClImportTensorHandlefactory for tensor import. * Add unit tests. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: I61884fed65e764ebd6985fe0833e43a7296d0641
2021-03-22Revert "Fix deserializer output binding tensorshape logic"Teresa Charlin
This reverts commit 4c10dfc213a59ec7bbf56b645e313083638b81a4. Fix for IVGCVSW-5768 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7197067a7bb407ff9d35059289a31912592d3af4
2021-03-22Update ACL pin to ab8408872f49c9429c84d83de665c55e31a500b2Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ia6442ead871c829ce17b27fa225e3739c675d91f
2021-03-22Fold PAD into Pooling2dDiego Lopez Recas
Some models would add a PAD layer before a pooling when they can't express their padding configuration as SAME or VALID. Arm NN can merge the two because pooling layers are described with explicit padding. Signed-off-by: Diego Lopez Recas <diego.lopez.recas@gmail.com> Change-Id: Id048186db6a005e0257bfbc1406c3b0dab2cdd58
2021-03-19IVGCVSW-5760 Updating BuildGuideCrossCompilation.mdJan Eilers
* Doxygen can't handle code blocks right after a headline. It needs text or an empty line first Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ida56737b08cdd24046f17a1845ea31a12a60cf96
2021-03-18Update ACL pin to a50f19346c5b79e2743f882ce0c691c07076f207Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I18493c36ad87e87f836c42a0e72946332b8bcfa2
2021-03-16IVGCVSW-5778 Update README.md to say 16.04 LTS will be replaced by 18.04 LTS ↵Jim Flynn
from the 21.08 release Change-Id: I89ef90fe696706323715caa5f1a86b6dde978181 Signed-off-by: Jim Flynn <jim.flynn@arm.com>
2021-03-16IVGCVSW-5754 Change the behaviour of the AddBroadcastReshapeLayer ↵Finn Williams
Optimisation when the input is a const tensor Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I8b1357bdefc45880d064d7e448af364ac8644c0d
2021-03-15Update ACL pin to 42bd26560daa799dbb825a7c6aade61c7ca132a2Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I815f8d596caab053dc16d3c655bb1b92fbfbd531
2021-03-14GitHub#491 Adding QAsymmS8 to SerializerTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id0c1ce0ae8946bbc061f5c1f7a7798d3033e6ce4
2021-03-12IVGCVSW-5772 L2 pooling missing from armnnDeserializerTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I59bf2eade949043d1f498772fad66eda7d64a87f
2021-03-12IVGCVSW-5767 'Regression on SqueezeNet v1.1'Sadik Armagan
* Update ReduceLayer to use descriptor parameters Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I2ff240f63534de0fd647428cf411763829412443
2021-03-11IVGCVSW-5726 Implement Memory Import Functions in CltensorHandleDavid Monahan
* Contains a dummy import function as that will be implemented separately Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: If551b69e832c045c76775a7e5fa25647c2313908
2021-03-09IVGCVSW-5760 Updating BuildGuideCrossCompilation.mdColm Donelan
Updated many minor points in the document to correct errors or out of date references. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Ie42c186916d9dbff3114a810a97ed25da5a06ca5
2021-03-05IVGCVSW-5401 Remove unused variable.David Monahan
Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I127e6923f257bb4094485aa1716ead1067cf8d34
2021-03-04armnn_tfl_benchmark: allow string of backend to pass directlyKeith Mok
Instead of using the predefined backend ids, we should just pass the backend string directly to the optimator, otherwise we cannot use vendor specific backends or GpuAcc Signed-off-by: Keith Mok <ek9852@gmail.com> Change-Id: Ic52c81d48364a19f0fcc59bc3c975cf3bd740e21
2021-03-03IVGCVSW-5612 Fix tiny_wav2letter_relu_fixed_int8 delegate outputexperimental/abi-testsFinn Williams
* fix delegate perchannel quantization * change delegate to check reshape options before inputs * Add int8 "qsymms8" option to ExecuteNetwork * Add option to run ExecuteNetwork on tflite w/o delegate !referencetests:301301 Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: If3e12599b17aff1199d7ab0a55e1c901e480083d
2021-03-03Point readme files to latest doxygen documentationJan Eilers
* excluding our top level readme Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: I45b156c248178a141b8497dcc4d09148b67bf406
2021-03-03armnn_tfl_benchmark: Fix crashKeith Mok
The input tensor data pointer was passed incorrectly Signed-off-by: Keith Mok <ek9852@gmail.com> Change-Id: I03f872c57ec588fde0f7d444c80b38823ea4f9b4
2021-03-02Update ACL pin to b1ff7f7baafeba0443bd460793c60b1ce40a405fTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I8e617a6b67cb7188e389146875e41fe15542143b
2021-03-02Update ACL pin to 1055dc14c7812ea322947e5b4a0733fb7b206715Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I79694713bf67bccc61c376d439333c096448e258
2021-03-01Make SubgraphViewSelector give deterministic resultsRob Hughes
The subgraphs produced by SubgraphViewSelector were not deterministic as the order of the input slots, outputs slots and layers within each subgraph were determined by the pointer values of those objects, which are not guaranteed to be the same for each execution. This patch adds a post-processing sorting step based on the GUIDs of the layers and the slot indices so that the results will be the same for each execution. This makes debugging the optimised graph much easier as subsequent stages can also be deterministic. Change-Id: Ifbcb199733066f99e9f95808a8da22023e5944f1 Signed-off-by: Rob Hughes <robert.hughes@arm.com>
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