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2023-06-26IVGCVSW-7663 BuildGuideAndroidNDK script in armnnJohn Mcloughlin
* Removed Ubuntu 18.04 check for CMake 3.19 install Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: Ie1ffab5cc967849188e0684c7086296710d6d731
2023-06-22IVGCVSW-7785 Extend support for 3D tensors BATCH_TO_SPACE and SPACE_TO_BATCH ↵Teresa Charlin
in CpuRef * Both layers were assuming 4D tensors, now 3D is supported too. * Remove some unnecessary includes * Add Unit Tests Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7bdd11e4936a27cd97ec65fd915e6ccaa1494cff
2023-06-22Doxygen: Fix XML parsing error in Arm NN DoxygenNikhil Raj
* Currently Doxygen was failing with error XML Parsing Error: duplicate attribute in main. This is due to an obsolete align attribute * Fixed some minor warnings by closing the Third part tools table Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I08a0d734ee07aef6617aa23c6fbbc05fb20bdfe5
2023-06-22Bugfix: explicitly state the header to be included to replace deprecated oneFrancis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I3f2bc1afc9873ed111b756717b2e86acce268598
2023-06-22IVGCVSW-7785 BugFix: ExpandDims not working when batch!=1Teresa Charlin
* This commit fixes partially the ticket. In ToTensorInfo() we assume batch is 1 when it is unknown. We call OutputTensorInfoFromInputs() to amend this assumption/ However, this does not work for reshape layer. Therefore, we have to calculate the output shape in the ParseExpandDims(). Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iedc32a44b4ec0d8b7d2cc0b08f38f0776402f7bd
2023-06-19Update ACL pin to 043613fbb199e2c4fdd12c2c9a1785db9b0c45faNikhil Raj
* Break up Utils.h a bit to reduce unused code being included everywhere * Add FullyConnectedLayerInfo.h to ArmComputeUtils.hpp and remove Types.h * Add MatMulInfo.h to Neon and CL BatchMatMulWokloads Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I2fbe90cb40dc59add90735dafe9fef9aab3fbf06
2023-06-15Update ACL pin to bec9b032ddcff449c7ad40febbcab24c23ee58a0Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I999b5bedc34d626ed2907819e22cfb212837d514
2023-06-14Add DataType to .dot files for constant layersTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I399ed1205f14d4fdd1194026c7a66bf00a1dd68d
2023-06-14IVGCVSW-7791 Enable dynamic bias in Conv in CpuAcc and GpuAccKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I722a9e4f3dba2500c624c6326f74085277e0d631
2023-06-13IVGCVSW-7790 - Enable dynamic bias in DWConv in GpuAccKevin May
* Remove checks for ias being constant * Convert ARMNN_ASSERTS to throw Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I009f4008393502bd9e30269151ad935ef67f0bc1
2023-06-12Doxygen: Remove link to md files from excluded tests\ref/for/mainNikhil Raj
* These files are in tests which are excluded from doxygen * Add deprecated lists to doxygen Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I760c317b9454dd32ea924d1a1805d05919ead9b1
2023-06-12Update ACL pin to 08dfba38b99abcf12db39d6650e4e3758f1bd0b4Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I396178fe994278bdcfb62696d8066e487fb7905d
2023-06-09Fix ArmNN Operator table layout in doxygenNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I57ac5bd616b445e84ba12ef4189783943421ddb0
2023-06-09IVGCVSW-7691 Replace asserts with exceptions in Ref GatherKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: If6731b4757257d983c09210b50315cd5d9837e20
2023-06-08Fix issue with ExecuteNetwork when running with tflite executorNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Id404893c47d43dafa743f4b9524001072b426509
2023-06-08Update ACL pin to 6c7cf31655ebc65108f91df946904cc83e1b42f5Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ic39da278d89da1268a461a33f6a45595417c890b
2023-06-07IVGCVSW-7789 Enable dynamic bias in Depthwise Convolution in CpuAccTeresa Charlin
* Dynamic bias are supported by CpuAcc for this layer * Indentation and const modifiers minor changes Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I3b25f14feea55f746c254a832d97e21a1551ca36
2023-06-07Fix incorrect validation of Unidirectional Sequence LSTM on Cl and NeonNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I54c60fb98b9c560c300572f46d42b13aec7e402e
2023-06-07Update ACL pin to 48c0ed9d6298dfcc2bf37ac85c168fc7d41ee803Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ib9caa8d42969c584d904dfe922ebb9bf36643eee
2023-06-02Update ACL pin to df5d9878008be9b60586df97ebfff197abb5195eNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Idc72ddfeb7ff9c96620287e0fd47ae29e1ae4852
2023-06-01Update ACL pin to 545358ea7e65abfba6db5b194264584f1e54cc96Teresa Charlin
* Fix number of dimensions changed after transpose Change-Id: I5943399462e21ee56351289802687f47f3d74b3a Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I9c0688ee28210a0fd5f575a72c4774df66ff60c8
2023-05-25Update ACL pin to 6c113ed1a95a08d17c2d556bd7b03c901512a34fNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I0b9ffcef9d1fddba17edc1a3446d56fa1fa24a31
2023-05-23MLCE-1022 Fix failure on UnidirectionalSequenceLstm OperatorNarumol Prangnawarat
* Fix failure to parse UnidirectionalSequenceLstm Operator on CpuAcc * Fix failure to parse UnidirectionalSequenceLstm Operator on GpuAcc * Fix IsLayerSupported tests when there are multiple otutputs Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ia690f34d3c7fae87bd36c97056a3ff71baa865f6
2023-05-23BugFix: check for options!=null before adding fused activation in TfLite parserTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I96fd26559450690fbe99a0e8fbe193ddf5d3a34b
2023-05-23IVGCVSW-7732 Enable dynamic bias in FullyConnected in CpuAcc and GpuAccTeresa Charlin
* Dynamic bias are supported by ACL for this layer. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I428bd42a97e0c26c72f9925e3cb209c2fc9a650d
2023-05-23Update ACL pin to 1355ec4797cd77060af51c8b27d99ea1d25c08daNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Idf19ffc9e8c5c386b6a5b134cda16de2ff31b449
2023-05-22Add SqDiff, Power and Ceil to TypeUtils.hppTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ia026d7a9c71f2cede3e9b3d2c9a92c1781ec96a3
2023-05-18IVGCVSW-7735 Opaque Delegate CleanupRyan OShea
* Move TFL_TheStableDelegate to opaque/armnn_delegate_external.cpp * Change TFL_TheStableDelegate to extern variable * Remove duplicated opaque test sources * Add support for missing Fill operator * Enable support for Mirror Pad * Fix failing Split tests Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I7f8d8b4269bb4fbe27b6f47709cbd828554d37d8
2023-05-18IVGCVSW-7400 POW IVGCVSW-7278 SQUARED_DIFFERENCE to CpuAcc and GpuAccJohn Mcloughlin
* Add POW SQUARED_DIFFERENCE and Unit tests for CpuAcc and GpuAcc Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifa78af2a2fda2074586d8e4d9a506b1b13fa5755
2023-05-17IVGCVSW-7400 POW IVGCVSW-7278 SQUARED_DIFFERENCE.John Mcloughlin
* Added 2 new operators as ElementWiseBinary ops * Ref End to End and unit tests * Serialize and Deserialize tests * Delegate and Opaque Delegate tests * TfLite Parser tests Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I537158127f602f0c41ca0402aa31655cd3bd4281
2023-05-15Fix versions in Delegate Quick start guideNikhil Raj
* Fix tflite_runtime version * Fix Arm NN version * Fix Tf version Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I3baa3e2ccfcad524d81ee30b1e12468cd7be2cad
2023-05-11Revert "IVGCVSW-7454 Enable dynamic bias in CpuAcc and GpuAcc in Conv2d ↵TeresaARM
DWConv and FC" This reverts commit fecd9ed396705a17805ffc49839bd82ae24c892b. Reason for revert: IVGCVSW-7727 Dynamic bias CTS failing Change-Id: I53f67d60fca0e60a81298f90450ceef26b97c321 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2023-05-09IVGCVSW-7454 Enable dynamic bias in CpuAcc and GpuAcc in Conv2d DWConv and FCTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib6914a9a208475b68e969eba6f70fae4061efa9b
2023-05-09Removing "shiftID" from BackendProfilingCounterRegisterMockBackendTestNikhil Raj
This test case has caused several problems over the years. All the problems are around using counter indices to identify counters rather than names. Updating the test to check for registered counter names. Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ic5ebc9b2d53f2db301a3067ecce4befc14dcb8a5
2023-05-09IVGCVSW-7626 Change sequence of Interpreter BuildingNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I3f0e224c90a4eea9945183028c9de1b61e75e510
2023-05-09IVGCVSW-5846 Remove TODO statements from Armnn CodeDavid Monahan
* Removed all instances of TODO statements from comments * Removed statements are noted as part of IVGCVSW-5846 * Removed ProtoxtFixture.cpp from the Onnx Parser tests as it's not used Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ia0a15f8a0d4123c8831638634eaa0d1018c40e2c
2023-05-08IVGCVSW-7197 Bugfix: typos - member variables prefixed with p_ not m_Francis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I7df65ff96ce232dedd80debc34e23a595f99fd06
2023-05-08IVGCVSW-7454 Fix CpuAcc FC dynamic weightsTeresa Charlin
* Pass to ACL the flag for constant weights and bias in FC, conv and DWconv workloads Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iae2810c8d1a402d4afc1e757846665315a80d3ea
2023-05-08IVGCVSW-7454 Enable NonConstWeights in GpuAccTeresa Charlin
* Set flag for constant weights and bias in ACL tensorInfo in ACl workloads * Set flag for constant weights and bias in Unit Tests * Add to dot file for FullyConnected layer the constantWeights flag Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I87e1fef516ce4a8a59245dfdf7d92c153418e1d6
2023-05-08Improve reusability of code that is defined out by cmake build pathsRyan OShea
* Added new ARMNN_STUB_PROFILING and ARMNN_DISABLE_DYNAMIC_BACKEND defines to replace BUILD_BARE_METAL and BUILD_EXECUTE_NETWORK_STATIC * Add new CMake variables to disable sample apps and dynamic backends * Improve BUILD_SHARED_LIBS CMake variable * Add new archive output location to various libraries so that the static libraries appear in the same location as the shared libraries * Fixes for bare metal build * Add ARMNN_DISABLE_FILE_SYSTEM defines to missing locations Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: I1db9a8f483e7134bd261294b35240cf21b150d45
2023-05-08IVGCVSW-7485 Update operator support documentation for 23.05Matthew Sloyan
* Added CEIL and other missing operators to TfLiteParser and TfLite Delegate documentation. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ic30a3367a13d3b64aca2f7a8d8cc5b16616a0bcc
2023-05-08IVGCVSW-7626 Add Execute Network for Opaque DelegateNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ibdded86713368ecfdf31c4118dfe8a3404d1e3b8
2023-05-08IVGCVSW-7308 Add GpuAcc Batch MatMul workloadTeresa Charlin
* Call dedicated MatMul kernel in ACL * Add int8 tests * Add int8 to documentation * Force tensors to be dynamic (nonConst) as per request of ACL Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7b7ac20deec8637dc46ca990d339d92c4587cbe4
2023-05-08IVGCVSW-7307 Add CpuAcc Batch MatMul WorkloadTeresa Charlin
* Call dedicated MatMul kernel in ACL * Add int8 tests * Add int8 to documentation * Force tensors to be dynamic (nonConst) as per request of ACL Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I992ae9aae1174214607bf29305f21cdeaf3fdc1b
2023-05-08BugFix: Calculate explicit padding for Delegate Transpose Convolution using ↵Matthew Sloyan
output size * Added fix to Classic and Opaque Delegate which now matches the TfLiteParser. * Removed uses of single parameter IsValid function in classic Convolution visit functions. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I5be91ec25c11354a9b8472d0a429e71e02df6f9c
2023-05-06Update ACL pin to 23.05 release branchNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Iadba213e78f4c7eed7d1eea2206dcd1d977446b5
2023-05-05MLCE-1050 Error handing Slice operatorsMike Kelly
* If the dimension Size[n] in a Slice is -1 then it should be treated as "InputShape[n] - Begin[n]" but the Delegate simply cast the Size to uint and treated it as 4294967295. * Added the layer name that includes the node index to the Slice to aid debugging. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I45fa88b24982c3c97f48d0dc05cf7d9bb6db4074
2023-05-05IVGCVSW-7423 Add ArmnnDelegatePluginNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ie02021ac56a512598760e4c6d05ef1a80f4aec8d
2023-05-05IVGCVSW-7618 Implement UnidirectionalSequenceLstm operator for Opaque DelegateMatthew Sloyan
* Intermediate tensors aren't accessible through the new Opaque interface yet, so we have to cast to TfLiteNode for now. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ifd91131e5d5ff6cc057b80729fea9afa68ed240b
2023-05-05IVGCVSW-7484 Update versions in Arm NN for 23.05Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ib0d7835355e82d94b66b27a25b56b788c4606ae8
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