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| author | James Conroy <james.conroy@arm.com> | 2018-10-31 11:47:53 +0000 |
|---|---|---|
| committer | James Conroy <james.conroy@arm.com> | 2018-10-31 12:06:53 +0000 |
| commit | 45a9b775bf63283320315d90e4e9a6c641df6e20 (patch) | |
| tree | e1f0d33d98410255a6804ea9cccf16805fc6080f /tests/TfLiteVGG16Quantized-Armnn/Validation.txt | |
| parent | d84216a013445e86183e39c8b5b904836c71a95b (diff) | |
| download | armnn-45a9b775bf63283320315d90e4e9a6c641df6e20.tar.gz | |
IVGCVSW-2102: Fix Pooling2D CpuRef indexing bug
* Fixes bug when calcuating indexes for NHWC in
Pooling2D CpuRef implementation, it now uses
TensorBufferArrayView.
* Adds 2-Channel unit tests for Pooling2d on CpuRef,
Cl and Neon. The single channel tests were not
properly exercising Pooling2d using NHWC data layout.
* Refactors Pooling2D NHWC tests so that the input and
output data are permuted to NHWC when necessary,
instead of hard coding the data in NHWC format.
Change-Id: I5b9d41ed425ff283ea8c8ef6b1266ae0bc80f43b
Diffstat (limited to 'tests/TfLiteVGG16Quantized-Armnn/Validation.txt')
0 files changed, 0 insertions, 0 deletions