IVGCVSW-5091 Add Logical ops frontend and ref impl

* Add frontend and reference implementation for logical
  ops NOT, AND, OR.
* Unary NOT uses existing ElementwiseUnary layer and
  ElementwiseUnary descriptor.
* Binary AND/OR uses new layer LogicalBinary and new
  LogicalBinary descriptor.
* Add serialization/deserializion support and add missing
  ElementwiseUnary deserializer code.
* Add additional Boolean decoder in BaseIterator.hpp.

Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: Id343b01174053a166de1b98b6175e04a5065f720

1 files changed, 34 insertions, 0 deletions

diff --git a/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp b/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp
new file mode 100644
index 0000000000..4d6baf5fa4
--- /dev/null
+++ b/src/backends/reference/workloads/RefLogicalBinaryWorkload.hpp
@@ -0,0 +1,34 @@
+//
+// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "BaseIterator.hpp"
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+
+class RefLogicalBinaryWorkload : public BaseWorkload<LogicalBinaryQueueDescriptor>
+{
+public:
+    using BaseWorkload<LogicalBinaryQueueDescriptor>::m_Data;
+
+    RefLogicalBinaryWorkload(const LogicalBinaryQueueDescriptor& descriptor, const WorkloadInfo& info);
+    void PostAllocationConfigure() override;
+    virtual void Execute() const override;
+
+private:
+    using InType  = bool;
+    using OutType = bool;
+
+    std::unique_ptr<Decoder<InType>>  m_Input0;
+    std::unique_ptr<Decoder<InType>>  m_Input1;
+    std::unique_ptr<Encoder<OutType>> m_Output;
+};
+
+} // namespace armnn