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authorsaoste01 <saoirse.stewart@arm.com>2019-01-08 13:55:59 +0000
committerMatteo Martincigh <matteo.martincigh@arm.com>2019-01-09 11:51:17 +0000
commit9292aa3c71301a8989caaed6c9ad18e2190a8baa (patch)
tree92814c538086335d11843d7380b5ba164fcb4e90 /src/backends/cl/workloads/ClMinimumWorkload.cpp
parent54b2169989fa9916565fb8a2edf717c6c93923d9 (diff)
downloadarmnn-9292aa3c71301a8989caaed6c9ad18e2190a8baa.tar.gz
IVGCVSW-2438 Add Minimum operator support (CL)
* Added CL unit tests Change-Id: Ia4af49b133774141384a177f5b042e65764bf682
Diffstat (limited to 'src/backends/cl/workloads/ClMinimumWorkload.cpp')
-rw-r--r--src/backends/cl/workloads/ClMinimumWorkload.cpp58
1 files changed, 58 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/ClMinimumWorkload.cpp b/src/backends/cl/workloads/ClMinimumWorkload.cpp
new file mode 100644
index 0000000000..5f8dfdb8eb
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+++ b/src/backends/cl/workloads/ClMinimumWorkload.cpp
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+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClMinimumWorkload.hpp"
+
+#include "ClWorkloadUtils.hpp"
+
+#include <aclCommon/ArmComputeUtils.hpp>
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+
+#include <backendsCommon/CpuTensorHandle.hpp>
+
+#include <cl/ClLayerSupport.hpp>
+#include <cl/ClTensorHandle.hpp>
+#include <cl/ClLayerSupport.hpp>
+
+namespace armnn
+{
+
+using namespace armcomputetensorutils;
+
+arm_compute::Status ClMinimumWorkloadValidate(const TensorInfo& input0,
+ const TensorInfo& input1,
+ const TensorInfo& output)
+{
+ const arm_compute::TensorInfo aclInput0Info = BuildArmComputeTensorInfo(input0);
+ const arm_compute::TensorInfo aclInput1Info = BuildArmComputeTensorInfo(input1);
+ const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output);
+
+ const arm_compute::Status aclStatus = arm_compute::CLElementwiseMin::validate(&aclInput0Info,
+ &aclInput1Info,
+ &aclOutputInfo);
+
+ return aclStatus;
+}
+
+ClMinimumWorkload::ClMinimumWorkload(const MinimumQueueDescriptor& descriptor,
+ const WorkloadInfo& info)
+ : BaseWorkload<MinimumQueueDescriptor>(descriptor, info)
+{
+ m_Data.ValidateInputsOutputs("ClMinimumWorkload", 2, 1);
+
+ arm_compute::ICLTensor& input0 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+ arm_compute::ICLTensor& input1 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor();
+ arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+ m_MinimumLayer.configure(&input0, &input1, &output);
+}
+
+void ClMinimumWorkload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT_CL("ClMinimumWorkload_Execute");
+ RunClFunction(m_MinimumLayer, CHECK_LOCATION());
+}
+
+} //namespace armnn