Merge 'main' onto 'experimental/GpuFsa'.

  * I6c71be11e9b73694747b27fe9febab8d9669b4d4

Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: Iccaf50e2484559979d801ee9d0e130e848554733

4 files changed, 43 insertions, 17 deletions

diff --git a/delegate/src/armnn_delegate.cpp b/delegate/src/armnn_delegate.cpp
index 4d95522dbd..aa6c1be37d 100644
--- a/delegate/src/armnn_delegate.cpp
+++ b/delegate/src/armnn_delegate.cpp
@@ -137,13 +137,12 @@ Delegate::Delegate(armnnDelegate::DelegateOptions options)
     m_Options(std::move(options))
 {
     // Configures logging for ARMNN
-    if (options.IsLoggingEnabled())
+    if (m_Options.IsLoggingEnabled())
     {
-        armnn::ConfigureLogging(true, true, options.GetLoggingSeverity());
+        armnn::ConfigureLogging(true, true, m_Options.GetLoggingSeverity());
     }
-
     // Create ArmNN Runtime
-    m_Runtime = armnn::IRuntime::Create(options.GetRuntimeOptions());
+    m_Runtime = armnn::IRuntime::Create(m_Options.GetRuntimeOptions());
 
     std::vector<armnn::BackendId> backends;
     if (m_Runtime)
@@ -206,8 +205,20 @@ TfLiteIntArray* Delegate::IdentifyOperatorsToDelegate(TfLiteContext* tfLiteConte
             continue;
         }
 
-        if (ArmnnSubgraph::VisitNode(
-                   delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex) != kTfLiteOk)
+        TfLiteStatus visitStatus;
+
+        try
+        {
+            visitStatus = ArmnnSubgraph::VisitNode(
+                    delegateData, tfLiteContext, tfLiteRegistration, tfLiteNode, nodeIndex);
+        }
+        catch(std::exception& ex)
+        {
+            ARMNN_LOG(error) << "ArmNN Failed to visit node with error: " << ex.what();
+            visitStatus = kTfLiteError;
+        }
+
+        if ( visitStatus != kTfLiteOk)
         {
             // node is not supported by ArmNN
             unsupportedOperators.insert(tfLiteRegistration->builtin_code);
@@ -377,7 +388,7 @@ ArmnnSubgraph* ArmnnSubgraph::Create(TfLiteContext* tfLiteContext,
         ARMNN_LOG(info) << "Optimize ArmnnSubgraph time: " << std::setprecision(2)
                         << std::fixed << armnn::GetTimeDuration(optimizeStartTime).count() << " ms";
     }
-    catch (std::exception &ex)
+    catch (std::exception& ex)
     {
         std::stringstream exMessage;
         exMessage << "TfLiteArmnnDelegate: Exception (" << ex.what() << ") caught from optimize.";
diff --git a/delegate/src/test/BatchMatMulTest.cpp b/delegate/src/test/BatchMatMulTest.cpp
index e5cb976c45..d13d8dcf43 100644
--- a/delegate/src/test/BatchMatMulTest.cpp
+++ b/delegate/src/test/BatchMatMulTest.cpp
@@ -268,7 +268,7 @@ namespace armnnDelegate
     {
         // Set input data
         std::vector<int32_t> LHSInputShape { 2,2,2 };
-        std::vector<int32_t> RHSInputShape { 1,2,2 };
+        std::vector<int32_t> RHSInputShape { 2,2 };
         std::vector<int32_t> outputShape   { 2,2,2 };
 
         std::vector<float> LHSInputValues = { 1, 2,
@@ -670,4 +670,19 @@ namespace armnnDelegate
             BatchMatMul2DFp32SimpleAdjointTest(backends);
         }
     }
+    TEST_SUITE("BATCH_MATMUL_GpuAccTests")
+    {
+        TEST_CASE("BATCH_MATMUL_Fp32_GpuAccTests")
+        {
+            std::vector <armnn::BackendId> backends = {armnn::Compute::GpuAcc};
+            BatchMatMul2DFp32SimpleTest       (backends);
+            BatchMatMul3DFp32SimpleTest       (backends);
+            BatchMatMul3DFp32BatchTest        (backends);
+            BatchMatMul3DFp32BroadcastTest    (backends);
+            BatchMatMul3D2DFp32BroadcastTest  (backends);
+            BatchMatMul2DFp32TinyTest         (backends);
+            BatchMatMulNonSquareFp32Test      (backends);
+            BatchMatMul2DFp32SimpleAdjointTest(backends);
+        }
+    }
 }
diff --git a/delegate/src/test/ControlTest.cpp b/delegate/src/test/ControlTest.cpp
index 43491be982..18bbc5a9a8 100644
--- a/delegate/src/test/ControlTest.cpp
+++ b/delegate/src/test/ControlTest.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020,2023 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -286,7 +286,7 @@ TEST_CASE ("Concatenation_Three_Inputs_GpuAcc_Test")
     ConcatThreeInputsTest(backends);
 }
 
-TEST_CASE ("Concatenation_Axis_CpuRef_Test")
+TEST_CASE ("Concatenation_Axis_GpuAcc_Test")
 {
     std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     ConcatAxisTest(backends);
diff --git a/delegate/src/test/Convolution2dTest.cpp b/delegate/src/test/Convolution2dTest.cpp
index b2e5fad8df..10510792a1 100644
--- a/delegate/src/test/Convolution2dTest.cpp
+++ b/delegate/src/test/Convolution2dTest.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2020,2023 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -438,13 +438,13 @@ void TransposeConvFp32Test(std::vector<armnn::BackendId>& backends)
 TEST_SUITE("TransposeConv_CpuRef_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_CpuRef_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuRef};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_CpuRef_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuRef};
     TransposeConvInt8Test(backends);
@@ -455,13 +455,13 @@ TEST_CASE ("TransposeConv_Int8_Test")
 TEST_SUITE("TransposeConv_CpuAcc_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_CpuAcc_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuAcc};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_CpuAcc_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::CpuAcc};
     TransposeConvInt8Test(backends);
@@ -472,13 +472,13 @@ TEST_CASE ("TransposeConv_Int8_Test")
 TEST_SUITE("TransposeConv_GpuAcc_Test")
 {
 
-TEST_CASE ("TransposeConv_Fp32_Test")
+TEST_CASE ("TransposeConv_GpuAcc_Fp32_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     TransposeConvFp32Test(backends);
 }
 
-TEST_CASE ("TransposeConv_Int8_Test")
+TEST_CASE ("TransposeConv_GpuAcc_Int8_Test")
 {
     std::vector <armnn::BackendId> backends = {armnn::Compute::GpuAcc};
     TransposeConvInt8Test(backends);