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author | Narumol Prangnawarat <narumol.prangnawarat@arm.com> | 2021-08-12 14:48:15 +0100 |
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committer | Narumol Prangnawarat <narumol.prangnawarat@arm.com> | 2021-08-31 14:13:48 +0000 |
commit | 7684b18e8fec45355a49e7f7165c582efc553ab6 (patch) | |
tree | f79078cec5e14534b82effaa6f8c4b70c3fe6bff /delegate/src/DelegateUtils.hpp | |
parent | b338fb08cc77892f9cc19132421db06d77f9afde (diff) | |
download | armnn-7684b18e8fec45355a49e7f7165c582efc553ab6.tar.gz |
MLCE-530 Add support for UnidirectionalSequenceLstm to armnn delegate
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com>
Change-Id: Ib04f8d6b9e60a4204c56eba4c2ecd2b316509dcc
Diffstat (limited to 'delegate/src/DelegateUtils.hpp')
-rw-r--r-- | delegate/src/DelegateUtils.hpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/delegate/src/DelegateUtils.hpp b/delegate/src/DelegateUtils.hpp index 2d1651842a..8c7ba25e15 100644 --- a/delegate/src/DelegateUtils.hpp +++ b/delegate/src/DelegateUtils.hpp @@ -506,6 +506,13 @@ armnn::ConstTensor CreateConstTensor(const TfLiteTensor* tfLiteTensor, } } +armnn::ConstTensor* GetConstTensorForTfLiteTensor(const TfLiteTensor* tfLiteTensors, TfLiteNode* tfLiteNode, int index) +{ + const TfLiteTensor &tfLiteTensor = tfLiteTensors[tfLiteNode->inputs->data[index]]; + armnn::TensorInfo tensorInfo = GetTensorInfoForTfLiteTensor(tfLiteTensor); + return new armnn::ConstTensor(tensorInfo, tfLiteTensor.data.data); +} + void CalcPadding(uint32_t inputSize, uint32_t filterSize, uint32_t stride, @@ -561,6 +568,15 @@ TfLiteStatus ConnectConstant(armnn::IConnectableLayer* layer, return kTfLiteOk; } +bool IsOptionalOperandPresent(TfLiteNode* tfLiteNode, const int operandIndex) +{ + if (tfLiteNode->inputs->data[operandIndex] < 0) { + return true; + } + return false; + +} + TfLiteStatus ProcessInputs(armnn::IConnectableLayer* layer, armnnDelegate::DelegateData& delegateData, TfLiteContext* tfLiteContext, |