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| author | Mike Kelly <mike.kelly@arm.com> | 2022-05-06 12:14:16 +0100 |
|---|---|---|
| committer | mike.kelly <mike.kelly@arm.com> | 2022-05-06 19:26:17 +0000 |
| commit | 84d63785eb2dceba297a685ebd98f1d29be47326 (patch) | |
| tree | efc28e6c28df26bdf946de7923c4b2b554913e1d /delegate/src/Convolution.hpp | |
| parent | 727c2b577fb2df7d433866792f1561af4ce43505 (diff) | |
| download | armnn-84d63785eb2dceba297a685ebd98f1d29be47326.tar.gz | |
IVGCVSW-6929 Fix for segfault in tflite delegate
* It's possible that a model may have an input entry for bias tensors
but that the index for those is -1. If it's -1 then it's not present.
* Fixed logic error in IsOptionalOperandPresent: it returned false if
it was present and true if it was missing.
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I45ad8d8552122493c529b1a35a5689416ccfbb71
Diffstat (limited to 'delegate/src/Convolution.hpp')
| -rw-r--r-- | delegate/src/Convolution.hpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/delegate/src/Convolution.hpp b/delegate/src/Convolution.hpp index f02a56fc7d..3b23d6d500 100644 --- a/delegate/src/Convolution.hpp +++ b/delegate/src/Convolution.hpp @@ -35,7 +35,7 @@ TfLiteStatus VisitConv2dOperator(DelegateData& delegateData, armnn::Convolution2dDescriptor descriptor; const auto params = reinterpret_cast<TfLiteConvParams*>(tfLiteNode->builtin_data); - bool biasEnabled = tfLiteNode->inputs->size > 2; + bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); descriptor.m_StrideY = NonNegative(params->stride_height, nodeIndex); @@ -225,7 +225,7 @@ TfLiteStatus VisitConv3dOperator(DelegateData& delegateData, armnn::Convolution3dDescriptor descriptor; const auto params = reinterpret_cast<TfLiteConv3DParams*>(tfLiteNode->builtin_data); - bool biasEnabled = tfLiteNode->inputs->size == 3 ? true : false; + bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); descriptor.m_BiasEnabled = biasEnabled; descriptor.m_DataLayout = armnn::DataLayout::NDHWC; descriptor.m_StrideX = NonNegative(params->stride_width, nodeIndex); @@ -382,7 +382,7 @@ TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, } TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); - bool biasEnabled = tfLiteNode->inputs->size > 2; + bool biasEnabled = IsOptionalOperandPresent(tfLiteNode, 2); armnn::DepthwiseConvolution2dDescriptor descriptor; const auto params = reinterpret_cast<TfLiteDepthwiseConvParams*>(tfLiteNode->builtin_data); |