1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
|
/*
* Copyright (c) 2019 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#pragma once
#ifdef __ARM_FEATURE_SVE
template<>
template<typename T>
inline void TransformImpl<8, 2, false, 2, 2, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax)
{
uint16_t *master_outptr = reinterpret_cast<uint16_t *>(out);
const uint16_t *inptr = reinterpret_cast<const uint16_t *>(in);
for (int y=y0; y<ymax; y+=8)
{
const int height = ymax-y;
const long inwidth = (kmax - k0);
const long outwidth = ((inwidth + 1) / 2) * 16;
long inpos = 0;
long outpos = 0;
uint16_t *outptr = master_outptr;
master_outptr += outwidth;
const uint16_t *inptr0 = inptr + y * ldin + k0;
const uint16_t *inptr1 = inptr0 + ldin;
const uint16_t *inptr2 = inptr1 + ldin;
const uint16_t *inptr3 = inptr2 + ldin;
const uint16_t *inptr4 = inptr3 + ldin;
const uint16_t *inptr5 = inptr4 + ldin;
const uint16_t *inptr6 = inptr5 + ldin;
const uint16_t *inptr7 = inptr6 + ldin;
switch(height)
{
case 1:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z4.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"zip2 z9.s, z0.s, z4.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip1 z0.s, z8.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z1.s, z8.s, z4.s\n"
"zip1 z2.s, z9.s, z4.s\n"
"zip2 z3.s, z9.s, z4.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip1 z8.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip1 z10.s, z1.s, z4.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z4.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip1 z12.s, z2.s, z4.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip2 z13.s, z2.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z4.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"zip2 z15.s, z3.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 2:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z4.h, #0\n"
"mov z14.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip1 z8.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip1 z10.s, z1.s, z4.s\n"
"zip2 z11.s, z1.s, z4.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip1 z0.s, z8.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z1.s, z8.s, z4.s\n"
"zip1 z2.s, z9.s, z4.s\n"
"zip2 z3.s, z9.s, z4.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip1 z4.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z5.s, z10.s, z14.s\n"
"zip1 z6.s, z11.s, z14.s\n"
"zip2 z7.s, z11.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip1 z8.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip1 z12.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip2 z13.s, z2.s, z6.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"zip2 z15.s, z3.s, z7.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 3:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z4.h, #0\n"
"mov z14.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z4.s\n"
"zip2 z11.s, z1.s, z4.s\n"
"zip1 z12.s, z2.s, z4.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z0.s, z8.s, z12.s\n"
"zip2 z1.s, z8.s, z12.s\n"
"zip1 z2.s, z9.s, z13.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z3.s, z9.s, z13.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z4.s, z10.s, z14.s\n"
"zip2 z5.s, z10.s, z14.s\n"
"zip1 z6.s, z11.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z7.s, z11.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip1 z10.s, z1.s, z5.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z11.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip1 z12.s, z2.s, z6.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"zip2 z15.s, z3.s, z7.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 4:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z4.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"ld1h z3.h, p0/z, [%[inptr3], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z4.s\n"
"zip2 z11.s, z1.s, z4.s\n"
"zip1 z12.s, z2.s, z4.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z4.s\n"
"zip2 z15.s, z3.s, z4.s\n"
"zip1 z0.s, z8.s, z12.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z1.s, z8.s, z12.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z2.s, z9.s, z13.s\n"
"zip2 z3.s, z9.s, z13.s\n"
"zip1 z4.s, z10.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z5.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z6.s, z11.s, z15.s\n"
"zip2 z7.s, z11.s, z15.s\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z15.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 5:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z5.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"ld1h z3.h, p0/z, [%[inptr3], %[inpos], LSL #1]\n"
"ld1h z4.h, p0/z, [%[inptr4], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip1 z8.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z5.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z5.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z5.s\n"
"zip2 z15.s, z3.s, z5.s\n"
"zip1 z0.s, z8.s, z12.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z1.s, z8.s, z12.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z2.s, z9.s, z13.s\n"
"zip2 z3.s, z9.s, z13.s\n"
"zip1 z4.s, z10.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z5.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z6.s, z11.s, z15.s\n"
"zip2 z7.s, z11.s, z15.s\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z15.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 6:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z6.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"ld1h z3.h, p0/z, [%[inptr3], %[inpos], LSL #1]\n"
"ld1h z4.h, p0/z, [%[inptr4], %[inpos], LSL #1]\n"
"ld1h z5.h, p0/z, [%[inptr5], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip1 z8.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z9.s, z0.s, z4.s\n"
"zip1 z10.s, z1.s, z5.s\n"
"zip2 z11.s, z1.s, z5.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z6.s\n"
"zip2 z15.s, z3.s, z6.s\n"
"zip1 z0.s, z8.s, z12.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z1.s, z8.s, z12.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z2.s, z9.s, z13.s\n"
"zip2 z3.s, z9.s, z13.s\n"
"zip1 z4.s, z10.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z5.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z6.s, z11.s, z15.s\n"
"zip2 z7.s, z11.s, z15.s\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z15.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
case 7:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"mov z7.h, #0\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"ld1h z3.h, p0/z, [%[inptr3], %[inpos], LSL #1]\n"
"ld1h z4.h, p0/z, [%[inptr4], %[inpos], LSL #1]\n"
"ld1h z5.h, p0/z, [%[inptr5], %[inpos], LSL #1]\n"
"ld1h z6.h, p0/z, [%[inptr6], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z7.s\n"
"zip2 z15.s, z3.s, z7.s\n"
"zip1 z0.s, z8.s, z12.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z1.s, z8.s, z12.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z2.s, z9.s, z13.s\n"
"zip2 z3.s, z9.s, z13.s\n"
"zip1 z4.s, z10.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z5.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z6.s, z11.s, z15.s\n"
"zip2 z7.s, z11.s, z15.s\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z15.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
default:
case 8:
__asm __volatile(
"1:\n"
"whilelt p0.h, %[inpos], %[inwidth]\n"
"b.none 2f\n"
"ld1h z0.h, p0/z, [%[inptr0], %[inpos], LSL #1]\n"
"ld1h z1.h, p0/z, [%[inptr1], %[inpos], LSL #1]\n"
"ld1h z2.h, p0/z, [%[inptr2], %[inpos], LSL #1]\n"
"ld1h z3.h, p0/z, [%[inptr3], %[inpos], LSL #1]\n"
"ld1h z4.h, p0/z, [%[inptr4], %[inpos], LSL #1]\n"
"ld1h z5.h, p0/z, [%[inptr5], %[inpos], LSL #1]\n"
"ld1h z6.h, p0/z, [%[inptr6], %[inpos], LSL #1]\n"
"ld1h z7.h, p0/z, [%[inptr7], %[inpos], LSL #1]\n"
"inch %[inpos], all, mul #1\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p0.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p1.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z14.s, z3.s, z7.s\n"
"zip2 z15.s, z3.s, z7.s\n"
"zip1 z0.s, z8.s, z12.s\n"
"whilelt p2.h, %[outpos], %[outwidth]\n"
"zip2 z1.s, z8.s, z12.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z2.s, z9.s, z13.s\n"
"zip2 z3.s, z9.s, z13.s\n"
"zip1 z4.s, z10.s, z14.s\n"
"whilelt p3.h, %[outpos], %[outwidth]\n"
"zip2 z5.s, z10.s, z14.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z6.s, z11.s, z15.s\n"
"zip2 z7.s, z11.s, z15.s\n"
"zip1 z8.s, z0.s, z4.s\n"
"whilelt p4.h, %[outpos], %[outwidth]\n"
"zip2 z9.s, z0.s, z4.s\n"
"inch %[outpos], all, mul #1\n"
"zip1 z10.s, z1.s, z5.s\n"
"st1h z8.h, p0, [%[outptr]]\n"
"zip2 z11.s, z1.s, z5.s\n"
"zip1 z12.s, z2.s, z6.s\n"
"whilelt p5.h, %[outpos], %[outwidth]\n"
"zip2 z13.s, z2.s, z6.s\n"
"st1h z9.h, p1, [%[outptr], #1, MUL VL]\n"
"zip1 z14.s, z3.s, z7.s\n"
"inch %[outpos], all, mul #1\n"
"zip2 z15.s, z3.s, z7.s\n"
"st1h z10.h, p2, [%[outptr], #2, MUL VL]\n"
"whilelt p6.h, %[outpos], %[outwidth]\n"
"st1h z11.h, p3, [%[outptr], #3, MUL VL]\n"
"inch %[outpos], all, mul #1\n"
"st1h z12.h, p4, [%[outptr], #4, MUL VL]\n"
"whilelt p7.h, %[outpos], %[outwidth]\n"
"inch %[outpos], all, mul #1\n"
"st1h z13.h, p5, [%[outptr], #5, MUL VL]\n"
"st1h z14.h, p6, [%[outptr], #6, MUL VL]\n"
"st1h z15.h, p7, [%[outptr], #7, MUL VL]\n"
"addvl %[outptr], %[outptr], #8\n"
"b 1b\n"
"2:\n"
: [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7)
: [outwidth] "r" (outwidth), [inwidth] "r" (inwidth)
: "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory"
);
break;
}
}
}
#endif // __ARM_FEATURE_SVE
|
