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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp180
1 files changed, 90 insertions, 90 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp
index f9619b9eb2..e0acb7ac02 100644
--- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp
@@ -47,23 +47,23 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl(
"blt 7f\n"
"1:" // 4-vectors of channels
"mov w20, #0xff800000\n"
- "dup v6.4s, w20\n"
+ "dup v7.4s, w20\n"
"mov x19, %x[inptrs]\n"
- "dup v5.4s, w20\n"
+ "dup v6.4s, w20\n"
"lsr x24, %x[n_valid_cells], #0x2\n"
+ "dup v5.4s, w20\n"
"dup v4.4s, w20\n"
- "dup v3.4s, w20\n"
"cbz x24, 4f\n"
"ldp x23, x22, [x19, #0x0]\n"
"ldp x21, x20, [x19, #0x10]\n"
"add x19, x19, #0x20\n"
"subs x24, x24, #0x1\n"
- "ldr q2, [x23, x28]\n"
- "ldr q1, [x22, x28]\n"
- "ldr q0, [x21, x28]\n"
- "ldr q31, [x20, x28]\n"
- "ldr q30, [x23, x27]\n"
- "ldr q22, [x22, x27]\n"
+ "ldr q3, [x23, x28]\n"
+ "ldr q2, [x22, x28]\n"
+ "ldr q1, [x21, x28]\n"
+ "ldr q0, [x20, x28]\n"
+ "ldr q31, [x23, x27]\n"
+ "ldr q30, [x22, x27]\n"
"ldr q29, [x21, x27]\n"
"ldr q28, [x20, x27]\n"
"ldr q27, [x23, x26]\n"
@@ -76,47 +76,47 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl(
"ldr q16, [x20, x25]\n"
"beq 3f\n"
"2:" // 4-vectors of channels: 4 inputs loop
- "fmax v23.4s, v2.4s, v1.4s\n"
+ "fmax v23.4s, v3.4s, v2.4s\n"
"ldp x23, x22, [x19, #0x0]\n"
"subs x24, x24, #0x1\n"
- "fmax v19.4s, v0.4s, v31.4s\n"
+ "fmax v19.4s, v1.4s, v0.4s\n"
"ldp x21, x20, [x19, #0x10]\n"
- "fmax v22.4s, v30.4s, v22.4s\n"
"add x19, x19, #0x20\n"
+ "fmax v22.4s, v31.4s, v30.4s\n"
+ "ldr q3, [x23, x28]\n"
"fmax v18.4s, v29.4s, v28.4s\n"
- "ldr q2, [x23, x28]\n"
"fmax v21.4s, v27.4s, v21.4s\n"
+ "ldr q2, [x22, x28]\n"
"fmax v17.4s, v26.4s, v17.4s\n"
- "ldr q1, [x22, x28]\n"
+ "ldr q1, [x21, x28]\n"
"fmax v20.4s, v25.4s, v20.4s\n"
- "ldr q0, [x21, x28]\n"
+ "ldr q0, [x20, x28]\n"
"fmax v16.4s, v24.4s, v16.4s\n"
- "ldr q31, [x20, x28]\n"
+ "ldr q31, [x23, x27]\n"
"fmax v19.4s, v23.4s, v19.4s\n"
- "ldr q30, [x23, x27]\n"
+ "ldr q30, [x22, x27]\n"
"fmax v18.4s, v22.4s, v18.4s\n"
- "ldr q22, [x22, x27]\n"
- "fmax v17.4s, v21.4s, v17.4s\n"
"ldr q29, [x21, x27]\n"
- "fmax v16.4s, v20.4s, v16.4s\n"
+ "fmax v17.4s, v21.4s, v17.4s\n"
"ldr q28, [x20, x27]\n"
- "fmax v6.4s, v6.4s, v19.4s\n"
+ "fmax v16.4s, v20.4s, v16.4s\n"
"ldr q27, [x23, x26]\n"
- "fmax v5.4s, v5.4s, v18.4s\n"
+ "fmax v7.4s, v7.4s, v19.4s\n"
"ldr q21, [x22, x26]\n"
- "fmax v4.4s, v4.4s, v17.4s\n"
+ "fmax v6.4s, v6.4s, v18.4s\n"
"ldr q26, [x21, x26]\n"
- "fmax v3.4s, v3.4s, v16.4s\n"
+ "fmax v5.4s, v5.4s, v17.4s\n"
"ldr q17, [x20, x26]\n"
+ "fmax v4.4s, v4.4s, v16.4s\n"
"ldr q25, [x23, x25]\n"
"ldr q20, [x22, x25]\n"
"ldr q24, [x21, x25]\n"
"ldr q16, [x20, x25]\n"
"bgt 2b\n"
"3:" // 4-vectors of channels: 4 inputs tail
- "fmax v23.4s, v2.4s, v1.4s\n"
- "fmax v19.4s, v0.4s, v31.4s\n"
- "fmax v22.4s, v30.4s, v22.4s\n"
+ "fmax v23.4s, v3.4s, v2.4s\n"
+ "fmax v19.4s, v1.4s, v0.4s\n"
+ "fmax v22.4s, v31.4s, v30.4s\n"
"fmax v18.4s, v29.4s, v28.4s\n"
"fmax v21.4s, v27.4s, v21.4s\n"
"fmax v17.4s, v26.4s, v17.4s\n"
@@ -126,33 +126,33 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl(
"fmax v18.4s, v22.4s, v18.4s\n"
"fmax v17.4s, v21.4s, v17.4s\n"
"fmax v16.4s, v20.4s, v16.4s\n"
- "fmax v6.4s, v6.4s, v19.4s\n"
- "fmax v5.4s, v5.4s, v18.4s\n"
- "fmax v4.4s, v4.4s, v17.4s\n"
- "fmax v3.4s, v3.4s, v16.4s\n"
+ "fmax v7.4s, v7.4s, v19.4s\n"
+ "fmax v6.4s, v6.4s, v18.4s\n"
+ "fmax v5.4s, v5.4s, v17.4s\n"
+ "fmax v4.4s, v4.4s, v16.4s\n"
"4:" // 4-vectors of channels: After loop
"ands x20, %x[n_valid_cells], #0x3\n"
"beq 6f\n"
"5:" // 4-vectors of channels: Single input loop
"ldr x23, [x19], #0x8\n"
"subs x20, x20, #0x1\n"
- "ldr q2, [x23, x28]\n"
- "fmax v6.4s, v6.4s, v2.4s\n"
- "ldr q30, [x23, x27]\n"
+ "ldr q3, [x23, x28]\n"
+ "fmax v7.4s, v7.4s, v3.4s\n"
+ "ldr q31, [x23, x27]\n"
"ldr q27, [x23, x26]\n"
- "fmax v5.4s, v5.4s, v30.4s\n"
+ "fmax v6.4s, v6.4s, v31.4s\n"
"ldr q25, [x23, x25]\n"
- "fmax v4.4s, v4.4s, v27.4s\n"
- "fmax v3.4s, v3.4s, v25.4s\n"
+ "fmax v5.4s, v5.4s, v27.4s\n"
+ "fmax v4.4s, v4.4s, v25.4s\n"
"bgt 5b\n"
"6:" // 4-vectors of channels: Single input loop: End
- "str q6, [%x[outptr], x28]\n"
- "str q5, [%x[outptr], x27]\n"
- "str q4, [%x[outptr], x26]\n"
- "str q3, [%x[outptr], x25]\n"
+ "str q7, [%x[outptr], x28]\n"
"add x28, x28, #0x40\n"
+ "str q6, [%x[outptr], x27]\n"
"add x27, x27, #0x40\n"
+ "str q5, [%x[outptr], x26]\n"
"add x26, x26, #0x40\n"
+ "str q4, [%x[outptr], x25]\n"
"add x25, x25, #0x40\n"
"sub %x[n_channels], %x[n_channels], #0x10\n"
"cmp %x[n_channels], #0x10\n"
@@ -163,49 +163,49 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl(
"blt 14f\n"
"8:" // Single vector of channels: Loop
"mov w19, #0xff800000\n"
- "dup v6.4s, w19\n"
+ "dup v7.4s, w19\n"
"mov x19, %x[inptrs]\n"
"lsr x24, %x[n_valid_cells], #0x2\n"
"cbz x24, 11f\n"
"ldp x23, x22, [x19, #0x0]\n"
- "subs x24, x24, #0x1\n"
"ldp x21, x20, [x19, #0x10]\n"
"add x19, x19, #0x20\n"
- "ldr q2, [x23, x28]\n"
- "ldr q1, [x22, x28]\n"
- "ldr q0, [x21, x28]\n"
- "ldr q31, [x20, x28]\n"
+ "subs x24, x24, #0x1\n"
+ "ldr q3, [x23, x28]\n"
+ "ldr q2, [x22, x28]\n"
+ "ldr q1, [x21, x28]\n"
+ "ldr q0, [x20, x28]\n"
"beq 10f\n"
"9:" // Single vector of channels: Loop: 4 inputs loop
- "fmax v23.4s, v2.4s, v1.4s\n"
+ "fmax v23.4s, v3.4s, v2.4s\n"
"ldp x23, x22, [x19, #0x0]\n"
"subs x24, x24, #0x1\n"
- "fmax v19.4s, v0.4s, v31.4s\n"
+ "fmax v19.4s, v1.4s, v0.4s\n"
"ldp x21, x20, [x19, #0x10]\n"
- "fmax v19.4s, v23.4s, v19.4s\n"
"add x19, x19, #0x20\n"
- "ldr q2, [x23, x28]\n"
- "fmax v6.4s, v6.4s, v19.4s\n"
- "ldr q1, [x22, x28]\n"
- "ldr q0, [x21, x28]\n"
- "ldr q31, [x20, x28]\n"
+ "fmax v19.4s, v23.4s, v19.4s\n"
+ "ldr q3, [x23, x28]\n"
+ "ldr q2, [x22, x28]\n"
+ "fmax v7.4s, v7.4s, v19.4s\n"
+ "ldr q1, [x21, x28]\n"
+ "ldr q0, [x20, x28]\n"
"bgt 9b\n"
"10:" // Single vector of channels: Loop: 4 inputs tail
- "fmax v23.4s, v2.4s, v1.4s\n"
- "fmax v19.4s, v0.4s, v31.4s\n"
+ "fmax v23.4s, v3.4s, v2.4s\n"
+ "fmax v19.4s, v1.4s, v0.4s\n"
"fmax v19.4s, v23.4s, v19.4s\n"
- "fmax v6.4s, v6.4s, v19.4s\n"
+ "fmax v7.4s, v7.4s, v19.4s\n"
"11:" // Single vector of channels: Loop: After loop
"ands x20, %x[n_valid_cells], #0x3\n"
"beq 13f\n"
"12:" // Single vector of channels: Loop: Single input loop
"ldr x23, [x19], #0x8\n"
"subs x20, x20, #0x1\n"
- "ldr q2, [x23, x28]\n"
- "fmax v6.4s, v6.4s, v2.4s\n"
+ "ldr q3, [x23, x28]\n"
+ "fmax v7.4s, v7.4s, v3.4s\n"
"bgt 12b\n"
"13:" // Single vector of channels: Loop: Single input loop: End
- "str q6, [%x[outptr], x28]\n"
+ "str q7, [%x[outptr], x28]\n"
"add x28, x28, #0x10\n"
"sub %x[n_channels], %x[n_channels], #0x4\n"
"cmp %x[n_channels], #0x4\n"
@@ -214,81 +214,81 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl(
"14:" // Oddments
"add %x[outptr], %x[outptr], x28\n"
"mov w19, #0xff800000\n"
- "dup v6.4s, w19\n"
+ "dup v7.4s, w19\n"
"mov x19, %x[inptrs]\n"
"lsr x24, %x[n_valid_cells], #0x2\n"
"cbz x24, 18f\n"
"15:" // Oddments: 4 inputs loop
- "movi v2.16b, #0x0\n"
+ "movi v3.16b, #0x0\n"
"ldp x23, x22, [x19, #0x0]\n"
"add x23, x23, x28\n"
- "movi v1.16b, #0x0\n"
+ "movi v2.16b, #0x0\n"
"ldp x21, x20, [x19, #0x10]\n"
- "movi v0.16b, #0x0\n"
+ "movi v1.16b, #0x0\n"
"add x19, x19, #0x20\n"
- "movi v31.16b, #0x0\n"
+ "movi v0.16b, #0x0\n"
"add x22, x22, x28\n"
"add x21, x21, x28\n"
"add x20, x20, x28\n"
"tbz %x[n_channels], #1, 16f\n"
- "ldr d2, [x23], #0x8\n"
- "ldr d1, [x22], #0x8\n"
- "ldr d0, [x21], #0x8\n"
- "ldr d31, [x20], #0x8\n"
+ "ldr d3, [x23], #0x8\n"
+ "ldr d2, [x22], #0x8\n"
+ "ldr d1, [x21], #0x8\n"
+ "ldr d0, [x20], #0x8\n"
"tbz %x[n_channels], #0, 17f\n"
- "ld1 { v2.s }[2], [x23], #0x4\n"
- "ld1 { v1.s }[2], [x22], #0x4\n"
- "ld1 { v0.s }[2], [x21], #0x4\n"
- "ld1 { v31.s }[2], [x20], #0x4\n"
+ "ld1 { v3.s }[2], [x23], #0x4\n"
+ "ld1 { v2.s }[2], [x22], #0x4\n"
+ "ld1 { v1.s }[2], [x21], #0x4\n"
+ "ld1 { v0.s }[2], [x20], #0x4\n"
"b 17f\n"
"16:" // Oddments: 4 inputs loop: Load: Bit 1: Unset
"tbz %x[n_channels], #0, 17f\n"
- "ldr s2, [x23], #0x4\n"
- "ldr s1, [x22], #0x4\n"
- "ldr s0, [x21], #0x4\n"
- "ldr s31, [x20], #0x4\n"
+ "ldr s3, [x23], #0x4\n"
+ "ldr s2, [x22], #0x4\n"
+ "ldr s1, [x21], #0x4\n"
+ "ldr s0, [x20], #0x4\n"
"17:" // Oddments: 4 inputs loop: Load: Bit 1: End
- "fmax v23.4s, v2.4s, v1.4s\n"
+ "fmax v23.4s, v3.4s, v2.4s\n"
"subs x24, x24, #0x1\n"
- "fmax v19.4s, v0.4s, v31.4s\n"
+ "fmax v19.4s, v1.4s, v0.4s\n"
"fmax v19.4s, v23.4s, v19.4s\n"
- "fmax v6.4s, v6.4s, v19.4s\n"
+ "fmax v7.4s, v7.4s, v19.4s\n"
"bgt 15b\n"
"18:" // Oddments: After loop
"ands x20, %x[n_valid_cells], #0x3\n"
"beq 22f\n"
"19:" // Oddments: Single input loop
- "movi v2.16b, #0x0\n"
+ "movi v3.16b, #0x0\n"
"ldr x23, [x19], #0x8\n"
"add x23, x23, x28\n"
"tbz %x[n_channels], #1, 20f\n"
- "ldr d2, [x23], #0x8\n"
+ "ldr d3, [x23], #0x8\n"
"tbz %x[n_channels], #0, 21f\n"
- "ld1 { v2.s }[2], [x23], #0x4\n"
+ "ld1 { v3.s }[2], [x23], #0x4\n"
"b 21f\n"
"20:" // Oddments: Single input loop: Load: Bit 1: Unset
"tbz %x[n_channels], #0, 21f\n"
- "ldr s2, [x23], #0x4\n"
+ "ldr s3, [x23], #0x4\n"
"21:" // Oddments: Single input loop: Load: Bit 1: End
- "fmax v6.4s, v6.4s, v2.4s\n"
+ "fmax v7.4s, v7.4s, v3.4s\n"
"subs x20, x20, #0x1\n"
"bgt 19b\n"
"22:" // Oddments: Single input loop: End
"tbz %x[n_channels], #1, 23f\n"
- "st1 { v6.d }[0], [%x[outptr]], #0x8\n"
+ "st1 { v7.d }[0], [%x[outptr]], #0x8\n"
"tbz %x[n_channels], #0, 24f\n"
- "st1 { v6.s }[2], [%x[outptr]], #0x4\n"
+ "st1 { v7.s }[2], [%x[outptr]], #0x4\n"
"b 24f\n"
"23:" // Oddments: Store: Bit 1: Unset
"tbz %x[n_channels], #0, 24f\n"
- "st1 { v6.s }[0], [%x[outptr]], #0x4\n"
+ "st1 { v7.s }[0], [%x[outptr]], #0x4\n"
"24:" // Oddments: Store: Bit 1: End
"25:" // End
: [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr)
: [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells)
- : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-05 10:31:53 +0000