diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp index 2410d38512..89cb2ec380 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp @@ -265,24 +265,24 @@ void a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "smlal2 v26.4s, v29.8h, v6.8h\n" "smlal v12.4s, v31.4h, v6.4h\n" "smlal v14.4s, v30.4h, v8.4h\n" - "sqdmulh v12.4s, v12.4s, v21.4s\n" + "sqrdmulh v12.4s, v12.4s, v21.4s\n" "smlal v16.4s, v28.4h, v8.4h\n" "smlal v18.4s, v28.4h, v7.4h\n" - "sqdmulh v14.4s, v14.4s, v21.4s\n" + "sqrdmulh v14.4s, v14.4s, v21.4s\n" "smlal2 v17.4s, v31.8h, v6.8h\n" "smlal2 v9.4s, v30.8h, v8.8h\n" - "sqdmulh v16.4s, v16.4s, v21.4s\n" + "sqrdmulh v16.4s, v16.4s, v21.4s\n" "smlal2 v10.4s, v28.8h, v8.8h\n" "smlal2 v26.4s, v28.8h, v7.8h\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" "and v29.16b, v12.16b, v24.16b\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "and v22.16b, v14.16b, v24.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "and v21.16b, v16.16b, v24.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v18.16b, v24.16b\n" - "sqdmulh v26.4s, v26.4s, v19.4s\n" + "sqrdmulh v26.4s, v26.4s, v19.4s\n" "sshr v29.4s, v29.4s, #0x1f\n" "and v19.16b, v17.16b, v23.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -491,24 +491,24 @@ void a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "smlal2 v26.4s, v29.8h, v6.8h\n" "smlal v12.4s, v31.4h, v6.4h\n" "smlal v14.4s, v30.4h, v8.4h\n" - "sqdmulh v12.4s, v12.4s, v21.4s\n" + "sqrdmulh v12.4s, v12.4s, v21.4s\n" "smlal v16.4s, v28.4h, v8.4h\n" "smlal v18.4s, v28.4h, v7.4h\n" - "sqdmulh v14.4s, v14.4s, v21.4s\n" + "sqrdmulh v14.4s, v14.4s, v21.4s\n" "smlal2 v17.4s, v31.8h, v6.8h\n" "smlal2 v9.4s, v30.8h, v8.8h\n" - "sqdmulh v16.4s, v16.4s, v21.4s\n" + "sqrdmulh v16.4s, v16.4s, v21.4s\n" "smlal2 v10.4s, v28.8h, v8.8h\n" "smlal2 v26.4s, v28.8h, v7.8h\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" "and v29.16b, v12.16b, v24.16b\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "and v22.16b, v14.16b, v24.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "and v21.16b, v16.16b, v24.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v18.16b, v24.16b\n" - "sqdmulh v26.4s, v26.4s, v19.4s\n" + "sqrdmulh v26.4s, v26.4s, v19.4s\n" "sshr v29.4s, v29.4s, #0x1f\n" "and v19.16b, v17.16b, v23.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" @@ -1041,22 +1041,22 @@ void a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "ld1 { v21.s }[0], [x12]\n" "ld1 { v24.s }[0], [x11]\n" "59:" // Oddments: Load requant params: Bit 2: End - "sqdmulh v12.4s, v12.4s, v21.4s\n" - "sqdmulh v14.4s, v14.4s, v21.4s\n" + "sqrdmulh v12.4s, v12.4s, v21.4s\n" + "sqrdmulh v14.4s, v14.4s, v21.4s\n" "add x10, x10, x14\n" "add x9, x9, x14\n" - "sqdmulh v16.4s, v16.4s, v21.4s\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v16.4s, v16.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" "add x28, x28, x14\n" "add x27, x27, x14\n" "and v29.16b, v12.16b, v24.16b\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "and v22.16b, v14.16b, v24.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "and v21.16b, v16.16b, v24.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v18.16b, v24.16b\n" - "sqdmulh v26.4s, v26.4s, v19.4s\n" + "sqrdmulh v26.4s, v26.4s, v19.4s\n" "sshr v29.4s, v29.4s, #0x1f\n" "and v19.16b, v17.16b, v23.16b\n" "sshr v22.4s, v22.4s, #0x1f\n" |