diff options
| author | alerah01 <alex.rahlis@arm.com> | 2022-02-28 06:38:08 +0200 |
|---|---|---|
| committer | Alex Rahlis <alex.rahlis@arm.com> | 2022-03-03 11:35:37 +0000 |
| commit | 4cbcb840caca1346de5f2271b67e4ede17b72734 (patch) | |
| tree | 8c6950076fc2dc0be087f725c927751891619120 /src/cpu/kernels/scale/sve | |
| parent | 298b2c0526615fc1f0242c2792fe2c51a4f0c44a (diff) | |
| download | ComputeLibrary-4cbcb840caca1346de5f2271b67e4ede17b72734.tar.gz | |
Removing SVE / SVE2 guards from decoupled kernels
Jira: COMPMID-5172
Signed-off-by: alerah01 <alex.rahlis@arm.com>
Change-Id: I1b9ace8e573f85830f29728a27adfe39a0cab113
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7241
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/kernels/scale/sve')
| -rw-r--r-- | src/cpu/kernels/scale/sve/fp16.cpp | 8 | ||||
| -rw-r--r-- | src/cpu/kernels/scale/sve/fp32.cpp | 6 | ||||
| -rw-r--r-- | src/cpu/kernels/scale/sve/integer.cpp | 6 | ||||
| -rw-r--r-- | src/cpu/kernels/scale/sve/qasymm8.cpp | 6 | ||||
| -rw-r--r-- | src/cpu/kernels/scale/sve/qasymm8_signed.cpp | 6 |
5 files changed, 12 insertions, 20 deletions
diff --git a/src/cpu/kernels/scale/sve/fp16.cpp b/src/cpu/kernels/scale/sve/fp16.cpp index 76e7735b8a..d08bfd8cdf 100644 --- a/src/cpu/kernels/scale/sve/fp16.cpp +++ b/src/cpu/kernels/scale/sve/fp16.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -22,7 +22,8 @@ * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -172,5 +173,4 @@ void fp16_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, co } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */
\ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/fp32.cpp b/src/cpu/kernels/scale/sve/fp32.cpp index 030e109cdf..98b343870f 100644 --- a/src/cpu/kernels/scale/sve/fp32.cpp +++ b/src/cpu/kernels/scale/sve/fp32.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -170,5 +170,3 @@ void fp32_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, co } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/integer.cpp b/src/cpu/kernels/scale/sve/integer.cpp index 486c674612..00a43922d9 100644 --- a/src/cpu/kernels/scale/sve/integer.cpp +++ b/src/cpu/kernels/scale/sve/integer.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -296,5 +296,3 @@ void s16_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, con } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/qasymm8.cpp b/src/cpu/kernels/scale/sve/qasymm8.cpp index c9122ad40b..09ef00a783 100644 --- a/src/cpu/kernels/scale/sve/qasymm8.cpp +++ b/src/cpu/kernels/scale/sve/qasymm8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -203,5 +203,3 @@ void qasymm8_sve_scale(const ITensor *src, ITensor *dst, const ITensor *offsets, } } // namespace cpu } // namespace arm_compute - -#endif // defined(ARM_COMPUTE_ENABLE_SVE)
\ No newline at end of file diff --git a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp index 0843e61fd4..63f515442b 100644 --- a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp +++ b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -203,5 +203,3 @@ void qasymm8_signed_sve_scale(const ITensor *src, ITensor *dst, const ITensor *o } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE
\ No newline at end of file |