diff options
author | Michalis Spyrou <michalis.spyrou@arm.com> | 2021-06-08 10:42:54 +0100 |
---|---|---|
committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2021-06-08 12:11:12 +0000 |
commit | 5e53fc65a6d7a966541c3020593eefc5222ef914 (patch) | |
tree | be36dff93dfe3daa26c605f9bf367cd44451df2e /src/core/cpu/kernels/add | |
parent | 8ae3cdadbc96910171d35abaab633be03b07d6f4 (diff) | |
download | ComputeLibrary-5e53fc65a6d7a966541c3020593eefc5222ef914.tar.gz |
Add guards on SVE kernels
Some compiling issues are reported when building through ArmNN.
Resolves: COMPMID-4569
Change-Id: If464fda9157fbdba678e54f07b235e3ef00ee51a
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5777
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/cpu/kernels/add')
-rw-r--r-- | src/core/cpu/kernels/add/sve/impl.cpp | 4 | ||||
-rw-r--r-- | src/core/cpu/kernels/add/sve/integer.cpp | 4 | ||||
-rw-r--r-- | src/core/cpu/kernels/add/sve/qasymm8.cpp | 2 | ||||
-rw-r--r-- | src/core/cpu/kernels/add/sve/qasymm8_signed.cpp | 2 | ||||
-rw-r--r-- | src/core/cpu/kernels/add/sve/qsymm16.cpp | 2 |
5 files changed, 9 insertions, 5 deletions
diff --git a/src/core/cpu/kernels/add/sve/impl.cpp b/src/core/cpu/kernels/add/sve/impl.cpp index d1660fe19e..cf9e301c29 100644 --- a/src/core/cpu/kernels/add/sve/impl.cpp +++ b/src/core/cpu/kernels/add/sve/impl.cpp @@ -21,6 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#if defined(__ARM_FEATURE_SVE) #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -134,4 +135,5 @@ template void add_same_sve<uint8_t>(const ITensor *src0, const ITensor *src1, IT template void add_same_sve<int16_t>(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window); template void add_same_sve<int32_t>(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window); } // namespace cpu -} // namespace arm_compute
\ No newline at end of file +} // namespace arm_compute +#endif /* defined(__ARM_FEATURE_SVE) */
\ No newline at end of file diff --git a/src/core/cpu/kernels/add/sve/integer.cpp b/src/core/cpu/kernels/add/sve/integer.cpp index 6dec140499..bd8179205b 100644 --- a/src/core/cpu/kernels/add/sve/integer.cpp +++ b/src/core/cpu/kernels/add/sve/integer.cpp @@ -21,6 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#if defined(__ARM_FEATURE_SVE) #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" @@ -196,4 +197,5 @@ void add_u8_s16_s16_sve(const ITensor *src0, const ITensor *src1, ITensor *dst, add_s16_u8_s16_sve(src1, src0, dst, policy, window); } } // namespace cpu -} // namespace arm_compute
\ No newline at end of file +} // namespace arm_compute +#endif /* defined(__ARM_FEATURE_SVE) */
\ No newline at end of file diff --git a/src/core/cpu/kernels/add/sve/qasymm8.cpp b/src/core/cpu/kernels/add/sve/qasymm8.cpp index c47b5abf8a..f6d1485e61 100644 --- a/src/core/cpu/kernels/add/sve/qasymm8.cpp +++ b/src/core/cpu/kernels/add/sve/qasymm8.cpp @@ -21,12 +21,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#if defined(__ARM_FEATURE_SVE2) #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" #include "arm_compute/core/utils/misc/Traits.h" #include "src/core/NEON/wrapper/intrinsics/intrinsics.h" -#if defined(__ARM_FEATURE_SVE2) #include "src/core/NEON/SVEMath.h" #include <arm_sve.h> diff --git a/src/core/cpu/kernels/add/sve/qasymm8_signed.cpp b/src/core/cpu/kernels/add/sve/qasymm8_signed.cpp index 75d0f75a65..8102aa5c65 100644 --- a/src/core/cpu/kernels/add/sve/qasymm8_signed.cpp +++ b/src/core/cpu/kernels/add/sve/qasymm8_signed.cpp @@ -21,12 +21,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#if defined(__ARM_FEATURE_SVE2) #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" #include "arm_compute/core/utils/misc/Traits.h" #include "src/core/NEON/wrapper/intrinsics/intrinsics.h" -#if defined(__ARM_FEATURE_SVE2) #include "src/core/NEON/SVEMath.h" #include <arm_sve.h> diff --git a/src/core/cpu/kernels/add/sve/qsymm16.cpp b/src/core/cpu/kernels/add/sve/qsymm16.cpp index c3b72a5e65..fb62257b0a 100644 --- a/src/core/cpu/kernels/add/sve/qsymm16.cpp +++ b/src/core/cpu/kernels/add/sve/qsymm16.cpp @@ -21,12 +21,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#if defined(__ARM_FEATURE_SVE2) #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensor.h" #include "arm_compute/core/Types.h" #include "arm_compute/core/utils/misc/Traits.h" #include "src/core/NEON/wrapper/intrinsics/intrinsics.h" -#if defined(__ARM_FEATURE_SVE2) #include "src/core/NEON/SVEMath.h" #include <arm_sve.h> |