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| author | Georgios Pinitas <georgios.pinitas@arm.com> | 2018-10-26 19:05:32 +0100 |
|---|---|---|
| committer | Georgios Pinitas <georgios.pinitas@arm.com> | 2018-11-08 12:00:31 +0000 |
| commit | 421405b6a21b124288a750e2da26dc01eb7391cb (patch) | |
| tree | 35f5655ce9d8b5921cb03630534f532e4eb47bf5 /src/core/NEON/kernels/arm_gemm/transforms | |
| parent | f1adf11c776aebaa8da1b8644a4ba2453afd2b81 (diff) | |
| download | ComputeLibrary-421405b6a21b124288a750e2da26dc01eb7391cb.tar.gz | |
COMPMID-1675: Add SVE support
Change-Id: I86679adff556b6ffc9929b35cbf1b59b3958bdb1
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/transforms')
6 files changed, 3097 insertions, 1 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/transforms/list.hpp b/src/core/NEON/kernels/arm_gemm/transforms/list.hpp index 8ad5b857fb..17328a5d6a 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/list.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/list.hpp @@ -23,9 +23,17 @@ */ #include "a32_interleave_6way_32bit.hpp" #include "a32_transpose_interleave_8way_32bit.hpp" +#ifdef __ARM_FEATURE_SVE +#include "sve_interleave_8way_32bit.hpp" +#include "sve_interleave_8way_block2_16bit.hpp" +#include "sve_interleave_8way_block2_32bit.hpp" +#include "sve_interleave_8way_block4_16bit.hpp" +#include "sve_interleave_8way_block4_8bit.hpp" +#else +#include "a64_interleave_8way_32bit.hpp" +#endif #include "a64_block16_interleave4_8bit.hpp" #include "a64_interleave_8way_16bit.hpp" -#include "a64_interleave_8way_32bit.hpp" #include "a64_interleave_8way_half_to_float.hpp" #include "a64_transpose_interleave_12way_16bit.hpp" #include "a64_transpose_interleave_12way_half_to_float.hpp" diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp new file mode 100644 index 0000000000..752e837f8d --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_32bit.hpp @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template<typename T> +inline void TransformImpl<8, 1, false, 4, 4, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint32_t *master_outptr = reinterpret_cast<uint32_t *>(out); + const uint32_t *inptr = reinterpret_cast<const uint32_t *>(in); + + for (int y=y0; y<ymax; y+=8) + { + const int height = ymax-y; + const long inwidth = (kmax - k0); + const long outwidth = inwidth * 8; + long inpos = 0; + long outpos = 0; + + uint32_t *outptr = master_outptr; + master_outptr += outwidth; + + const uint32_t *inptr0 = inptr + y * ldin + k0; + const uint32_t *inptr1 = inptr0 + ldin; + const uint32_t *inptr2 = inptr1 + ldin; + const uint32_t *inptr3 = inptr2 + ldin; + const uint32_t *inptr4 = inptr3 + ldin; + const uint32_t *inptr5 = inptr4 + ldin; + const uint32_t *inptr6 = inptr5 + ldin; + const uint32_t *inptr7 = inptr6 + ldin; + + switch(height) + { + case 1: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "zip1 z0.s, z8.s, z4.s\n" + "zip2 z1.s, z8.s, z4.s\n" + "zip1 z2.s, z9.s, z4.s\n" + "zip2 z3.s, z9.s, z4.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z4.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z4.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 2: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "mov z14.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z0.s, z8.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z1.s, z8.s, z4.s\n" + "zip1 z2.s, z9.s, z4.s\n" + "zip2 z3.s, z9.s, z4.s\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z14.s\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z10.s, z1.s, z5.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "zip1 z14.s, z3.s, z7.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z15.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 3: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "mov z14.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "zip1 z12.s, z2.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z14.s\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 4: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "ld1w z3.s, p0/z, [%[inptr3], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "zip1 z12.s, z2.s, z4.s\n" + "zip2 z13.s, z2.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z4.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 5: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z5.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "ld1w z3.s, p0/z, [%[inptr3], %[inpos], LSL #2]\n" + "ld1w z4.s, p0/z, [%[inptr4], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z11.s, z1.s, z5.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z12.s, z2.s, z5.s\n" + "zip2 z13.s, z2.s, z5.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z5.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z5.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 6: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z6.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "ld1w z3.s, p0/z, [%[inptr3], %[inpos], LSL #2]\n" + "ld1w z4.s, p0/z, [%[inptr4], %[inpos], LSL #2]\n" + "ld1w z5.s, p0/z, [%[inptr5], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z6.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 7: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z7.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "ld1w z3.s, p0/z, [%[inptr3], %[inpos], LSL #2]\n" + "ld1w z4.s, p0/z, [%[inptr4], %[inpos], LSL #2]\n" + "ld1w z5.s, p0/z, [%[inptr5], %[inpos], LSL #2]\n" + "ld1w z6.s, p0/z, [%[inptr6], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + default: + case 8: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "ld1w z0.s, p0/z, [%[inptr0], %[inpos], LSL #2]\n" + "ld1w z1.s, p0/z, [%[inptr1], %[inpos], LSL #2]\n" + "ld1w z2.s, p0/z, [%[inptr2], %[inpos], LSL #2]\n" + "ld1w z3.s, p0/z, [%[inptr3], %[inpos], LSL #2]\n" + "ld1w z4.s, p0/z, [%[inptr4], %[inpos], LSL #2]\n" + "ld1w z5.s, p0/z, [%[inptr5], %[inpos], LSL #2]\n" + "ld1w z6.s, p0/z, [%[inptr6], %[inpos], LSL #2]\n" + "ld1w z7.s, p0/z, [%[inptr7], %[inpos], LSL #2]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.s, %[outpos], %[outwidth]\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z12.s, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.s, %[outpos], %[outwidth]\n" + "incw %[outpos], all, mul #1\n" + "st1w z13.s, p5, [%[outptr], #5, MUL VL]\n" + "st1w z14.s, p6, [%[outptr], #6, MUL VL]\n" + "st1w z15.s, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_16bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_16bit.hpp new file mode 100644 index 0000000000..63c21be6bb --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_16bit.hpp @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template<typename T> +inline void TransformImpl<8, 2, false, 2, 2, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint16_t *master_outptr = reinterpret_cast<uint16_t *>(out); + const uint16_t *inptr = reinterpret_cast<const uint16_t *>(in); + + for (int y=y0; y<ymax; y+=8) + { + const int height = ymax-y; + const long inwidth = (kmax - k0); + const long outwidth = (inwidth * 8 + 1) / 2; + long inpos = 0; + long outpos = 0; + + uint16_t *outptr = master_outptr; + master_outptr += (outwidth * 2); + + const uint16_t *inptr0 = inptr + y * ldin + k0; + const uint16_t *inptr1 = inptr0 + ldin; + const uint16_t *inptr2 = inptr1 + ldin; + const uint16_t *inptr3 = inptr2 + ldin; + const uint16_t *inptr4 = inptr3 + ldin; + const uint16_t *inptr5 = inptr4 + ldin; + const uint16_t *inptr6 = inptr5 + ldin; + const uint16_t *inptr7 = inptr6 + ldin; + + switch(height) + { + case 1: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "inch %[inpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z0.s, z8.s, z4.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z4.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z11.s, z1.s, z4.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip1 z12.s, z2.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z13.s, z2.s, z4.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z4.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip2 z15.s, z3.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 2: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "inch %[inpos], all, mul #1\n" + "zip1 z10.s, z1.s, z4.s\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z11.s, z1.s, z4.s\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z0.s, z8.s, z4.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z4.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z4.s\n" + "incw %[outpos], all, mul #1\n" + "mov z14.h, #0\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip1 z4.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z5.s, z10.s, z14.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z6.s, z11.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 3: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip1 z10.s, z1.s, z4.s\n" + "inch %[inpos], all, mul #1\n" + "zip2 z11.s, z1.s, z4.s\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.s, z2.s, z4.s\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.s, z2.s, z4.s\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z0.s, z8.s, z12.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "mov z14.h, #0\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip1 z4.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z5.s, z10.s, z14.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z6.s, z11.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 4: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip1 z10.s, z1.s, z4.s\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip2 z11.s, z1.s, z4.s\n" + "inch %[inpos], all, mul #1\n" + "zip1 z12.s, z2.s, z4.s\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z13.s, z2.s, z4.s\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.s, z3.s, z4.s\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z15.s, z3.s, z4.s\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z0.s, z8.s, z12.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z7.s, z11.s, z15.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 5: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z5.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip2 z11.s, z1.s, z5.s\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip1 z12.s, z2.s, z5.s\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.s, z2.s, z5.s\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z14.s, z3.s, z5.s\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip2 z15.s, z3.s, z5.s\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z0.s, z8.s, z12.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z7.s, z11.s, z15.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 6: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z6.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.s, z2.s, z6.s\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip2 z13.s, z2.s, z6.s\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.s, z1.s, z5.s\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z14.s, z3.s, z6.s\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z15.s, z3.s, z6.s\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip1 z0.s, z8.s, z12.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z7.s, z11.s, z15.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 7: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z7.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "ld1h z6.h, p0/z, [%[inptr6]]\n" + "zip1 z10.s, z1.s, z5.s\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.s, z1.s, z5.s\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z12.s, z2.s, z6.s\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z13.s, z2.s, z6.s\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z0.s, z8.s, z12.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z1.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z15.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip2 z7.s, z11.s, z15.s\n" + "incw %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + default: + case 8: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "addvl %[inptr2], %[inptr2], #1\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "ld1h z6.h, p0/z, [%[inptr6]]\n" + "zip1 z10.s, z1.s, z5.s\n" + "ld1h z7.h, p0/z, [%[inptr7]]\n" + "zip2 z11.s, z1.s, z5.s\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z12.s, z2.s, z6.s\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z13.s, z2.s, z6.s\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "addvl %[inptr7], %[inptr7], #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip1 z0.s, z8.s, z12.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z1.s, z8.s, z12.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "zip1 z2.s, z9.s, z13.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z3.s, z9.s, z13.s\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "zip1 z4.s, z10.s, z14.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z5.s, z10.s, z14.s\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "zip1 z6.s, z11.s, z15.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z7.s, z11.s, z15.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "st1w z8.s, p0, [%[outptr]]\n" + "zip2 z9.s, z0.s, z4.s\n" + "st1w z9.s, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1w z10.s, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1w z11.s, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.s, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "st1w z12.s, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incw %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p1.s, %[outpos], %[outwidth]\n" + "st1w z13.s, p1, [%[outptr], #5, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p2.s, %[outpos], %[outwidth]\n" + "st1w z14.s, p2, [%[outptr], #6, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "whilelt p3.s, %[outpos], %[outwidth]\n" + "st1w z15.s, p3, [%[outptr], #7, MUL VL]\n" + "incw %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_32bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_32bit.hpp new file mode 100644 index 0000000000..4cc4311cee --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block2_32bit.hpp @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template<typename T> +inline void TransformImpl<8, 2, false, 4, 4, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint32_t *master_outptr = reinterpret_cast<uint32_t *>(out); + const uint32_t *inptr = reinterpret_cast<const uint32_t *>(in); + + for (int y=y0; y<ymax; y+=8) + { + const int height = ymax-y; + const long inwidth = (kmax - k0); + const long outwidth = (inwidth * 8 + 1) / 2; + long inpos = 0; + long outpos = 0; + + uint32_t *outptr = master_outptr; + master_outptr += (outwidth * 2); + + const uint32_t *inptr0 = inptr + y * ldin + k0; + const uint32_t *inptr1 = inptr0 + ldin; + const uint32_t *inptr2 = inptr1 + ldin; + const uint32_t *inptr3 = inptr2 + ldin; + const uint32_t *inptr4 = inptr3 + ldin; + const uint32_t *inptr5 = inptr4 + ldin; + const uint32_t *inptr6 = inptr5 + ldin; + const uint32_t *inptr7 = inptr6 + ldin; + + switch(height) + { + case 1: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "incw %[inpos], all, mul #1\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z0.d, z8.d, z4.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z4.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z4.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z11.d, z1.d, z4.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip1 z12.d, z2.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z14.d, z3.d, z4.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip2 z15.d, z3.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 2: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "incw %[inpos], all, mul #1\n" + "zip1 z10.d, z1.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z11.d, z1.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z0.d, z8.d, z4.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z4.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "mov z14.s, #0\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z14.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 3: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "zip1 z10.d, z1.d, z4.d\n" + "incw %[inpos], all, mul #1\n" + "zip2 z11.d, z1.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.d, z2.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "mov z14.s, #0\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z14.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 4: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "zip1 z10.d, z1.d, z4.d\n" + "ld1w z3.s, p0/z, [%[inptr3]]\n" + "zip2 z11.d, z1.d, z4.d\n" + "incw %[inpos], all, mul #1\n" + "zip1 z12.d, z2.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.d, z3.d, z4.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z15.d, z3.d, z4.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 5: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z5.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "incw %[inpos], all, mul #1\n" + "zip1 z10.d, z1.d, z5.d\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "zip2 z11.d, z1.d, z5.d\n" + "ld1w z3.s, p0/z, [%[inptr3]]\n" + "zip1 z12.d, z2.d, z5.d\n" + "ld1w z4.s, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.d, z2.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z14.d, z3.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip2 z15.d, z3.d, z5.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 6: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z6.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "incw %[inpos], all, mul #1\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "ld1w z3.s, p0/z, [%[inptr3]]\n" + "zip2 z13.d, z2.d, z6.d\n" + "ld1w z4.s, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z5.s, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z10.d, z1.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z14.d, z3.d, z6.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z15.d, z3.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 7: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z7.s, #0\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "incw %[inpos], all, mul #1\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1w z3.s, p0/z, [%[inptr3]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.d, z3.d, z7.d\n" + "ld1w z4.s, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z5.s, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1w z6.s, p0/z, [%[inptr6]]\n" + "zip1 z10.d, z1.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z13.d, z2.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + default: + case 8: + __asm __volatile( + "1:\n" + "whilelt p0.s, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "ld1w z0.s, p0/z, [%[inptr0]]\n" + "incw %[inpos], all, mul #1\n" + "ld1w z1.s, p0/z, [%[inptr1]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1w z2.s, p0/z, [%[inptr2]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "ld1w z3.s, p0/z, [%[inptr3]]\n" + "addvl %[inptr2], %[inptr2], #1\n" + "ld1w z4.s, p0/z, [%[inptr4]]\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1w z5.s, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1w z6.s, p0/z, [%[inptr6]]\n" + "zip1 z10.d, z1.d, z5.d\n" + "ld1w z7.s, p0/z, [%[inptr7]]\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z13.d, z2.d, z6.d\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z14.d, z3.d, z7.d\n" + "addvl %[inptr7], %[inptr7], #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip1 z0.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z1.d, z8.d, z12.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip1 z2.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z3.d, z9.d, z13.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z15.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_16bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_16bit.hpp new file mode 100644 index 0000000000..f493786320 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_16bit.hpp @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template<typename T> +inline void TransformImpl<8, 4, false, 2, 2, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint16_t *master_outptr = reinterpret_cast<uint16_t *>(out); + const uint16_t *inptr = reinterpret_cast<const uint16_t *>(in); + + for (int y=y0; y<ymax; y+=8) + { + const int height = ymax-y; + const long inwidth = (kmax - k0); + const long outwidth = (inwidth * 8 + 3) / 4; + long inpos = 0; + long outpos = 0; + + uint16_t *outptr = master_outptr; + master_outptr += (outwidth * 4); + + const uint16_t *inptr0 = inptr + y * ldin + k0; + const uint16_t *inptr1 = inptr0 + ldin; + const uint16_t *inptr2 = inptr1 + ldin; + const uint16_t *inptr3 = inptr2 + ldin; + const uint16_t *inptr4 = inptr3 + ldin; + const uint16_t *inptr5 = inptr4 + ldin; + const uint16_t *inptr6 = inptr5 + ldin; + const uint16_t *inptr7 = inptr6 + ldin; + + switch(height) + { + case 1: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "inch %[inpos], all, mul #1\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z0.d, z8.d, z4.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z4.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z4.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z11.d, z1.d, z4.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip1 z12.d, z2.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z14.d, z3.d, z4.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip2 z15.d, z3.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 2: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "inch %[inpos], all, mul #1\n" + "zip1 z10.d, z1.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z11.d, z1.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z0.d, z8.d, z4.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z4.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z4.d\n" + "incd %[outpos], all, mul #1\n" + "mov z14.h, #0\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z14.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 3: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip1 z10.d, z1.d, z4.d\n" + "inch %[inpos], all, mul #1\n" + "zip2 z11.d, z1.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.d, z2.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "mov z14.h, #0\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z14.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 4: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip1 z10.d, z1.d, z4.d\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip2 z11.d, z1.d, z4.d\n" + "inch %[inpos], all, mul #1\n" + "zip1 z12.d, z2.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z13.d, z2.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.d, z3.d, z4.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z15.d, z3.d, z4.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 5: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z5.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "zip1 z10.d, z1.d, z5.d\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "zip2 z11.d, z1.d, z5.d\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip1 z12.d, z2.d, z5.d\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip2 z13.d, z2.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip1 z14.d, z3.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip2 z15.d, z3.d, z5.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 6: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z6.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "zip2 z13.d, z2.d, z6.d\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z10.d, z1.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z14.d, z3.d, z6.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z15.d, z3.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 7: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z7.h, #0\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "zip1 z14.d, z3.d, z7.d\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1h z6.h, p0/z, [%[inptr6]]\n" + "zip1 z10.d, z1.d, z5.d\n" + "addvl %[inptr2], %[inptr2], #1\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip2 z13.d, z2.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z0.d, z8.d, z12.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z1.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z2.d, z9.d, z13.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip2 z3.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z4.d, z10.d, z14.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip2 z5.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z6.d, z11.d, z15.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip2 z7.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + default: + case 8: + __asm __volatile( + "1:\n" + "whilelt p0.h, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "ld1h z0.h, p0/z, [%[inptr0]]\n" + "inch %[inpos], all, mul #1\n" + "ld1h z1.h, p0/z, [%[inptr1]]\n" + "addvl %[inptr0], %[inptr0], #1\n" + "ld1h z2.h, p0/z, [%[inptr2]]\n" + "addvl %[inptr1], %[inptr1], #1\n" + "ld1h z3.h, p0/z, [%[inptr3]]\n" + "addvl %[inptr2], %[inptr2], #1\n" + "ld1h z4.h, p0/z, [%[inptr4]]\n" + "addvl %[inptr3], %[inptr3], #1\n" + "zip1 z8.d, z0.d, z4.d\n" + "ld1h z5.h, p0/z, [%[inptr5]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "ld1h z6.h, p0/z, [%[inptr6]]\n" + "zip1 z10.d, z1.d, z5.d\n" + "ld1h z7.h, p0/z, [%[inptr7]]\n" + "zip2 z11.d, z1.d, z5.d\n" + "addvl %[inptr4], %[inptr4], #1\n" + "zip1 z12.d, z2.d, z6.d\n" + "addvl %[inptr5], %[inptr5], #1\n" + "zip2 z13.d, z2.d, z6.d\n" + "addvl %[inptr6], %[inptr6], #1\n" + "zip1 z14.d, z3.d, z7.d\n" + "addvl %[inptr7], %[inptr7], #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip1 z0.d, z8.d, z12.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z1.d, z8.d, z12.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "zip1 z2.d, z9.d, z13.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z3.d, z9.d, z13.d\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "zip1 z4.d, z10.d, z14.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z5.d, z10.d, z14.d\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "zip1 z6.d, z11.d, z15.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z7.d, z11.d, z15.d\n" + "zip1 z8.d, z0.d, z4.d\n" + "st1d z8.d, p0, [%[outptr]]\n" + "zip2 z9.d, z0.d, z4.d\n" + "st1d z9.d, p1, [%[outptr], #1, MUL VL]\n" + "zip1 z10.d, z1.d, z5.d\n" + "st1d z10.d, p2, [%[outptr], #2, MUL VL]\n" + "zip2 z11.d, z1.d, z5.d\n" + "st1d z11.d, p3, [%[outptr], #3, MUL VL]\n" + "zip1 z12.d, z2.d, z6.d\n" + "whilelt p0.d, %[outpos], %[outwidth]\n" + "zip2 z13.d, z2.d, z6.d\n" + "st1d z12.d, p0, [%[outptr], #4, MUL VL]\n" + "zip1 z14.d, z3.d, z7.d\n" + "incd %[outpos], all, mul #1\n" + "zip2 z15.d, z3.d, z7.d\n" + "whilelt p1.d, %[outpos], %[outwidth]\n" + "st1d z13.d, p1, [%[outptr], #5, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p2.d, %[outpos], %[outwidth]\n" + "st1d z14.d, p2, [%[outptr], #6, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "whilelt p3.d, %[outpos], %[outwidth]\n" + "st1d z15.d, p3, [%[outptr], #7, MUL VL]\n" + "incd %[outpos], all, mul #1\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + + } + } +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_8bit.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_8bit.hpp new file mode 100644 index 0000000000..f1690baf43 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sve_interleave_8way_block4_8bit.hpp @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2018 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#ifdef __ARM_FEATURE_SVE + +template<> +template<typename T> +inline void TransformImpl<8, 4, false, 1, 1, false>::Transform(T *out, const T *in, int ldin, int y0, int ymax, int k0, int kmax) +{ + uint8_t *master_outptr = reinterpret_cast<uint8_t *>(out); + const uint8_t *inptr = reinterpret_cast<const uint8_t *>(in); + + for (int y=y0; y<ymax; y+=8) + { + const int height = ymax-y; + const long inwidth = (kmax - k0); + const long outwidth = ((inwidth + 3) / 4) * 32; + long inpos = 0; + long outpos = 0; + + uint8_t *outptr = master_outptr; + master_outptr += outwidth; + + const uint8_t *inptr0 = inptr + y * ldin + k0; + const uint8_t *inptr1 = inptr0 + ldin; + const uint8_t *inptr2 = inptr1 + ldin; + const uint8_t *inptr3 = inptr2 + ldin; + const uint8_t *inptr4 = inptr3 + ldin; + const uint8_t *inptr5 = inptr4 + ldin; + const uint8_t *inptr6 = inptr5 + ldin; + const uint8_t *inptr7 = inptr6 + ldin; + + switch(height) + { + case 1: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "zip1 z0.s, z8.s, z4.s\n" + "zip2 z1.s, z8.s, z4.s\n" + "zip1 z2.s, z9.s, z4.s\n" + "zip2 z3.s, z9.s, z4.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z4.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z4.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z4.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 2: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.b, #0\n" + "mov z14.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip1 z0.s, z8.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z1.s, z8.s, z4.s\n" + "zip1 z2.s, z9.s, z4.s\n" + "zip2 z3.s, z9.s, z4.s\n" + "zip1 z4.s, z10.s, z14.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z5.s, z10.s, z14.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z6.s, z11.s, z14.s\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z10.s, z1.s, z5.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "zip1 z14.s, z3.s, z7.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z15.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 3: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.b, #0\n" + "mov z14.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "zip1 z12.s, z2.s, z4.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z14.s\n" + "zip2 z7.s, z11.s, z14.s\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "incb %[outpos], all, mul #1\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 4: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z4.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "ld1b z3.b, p0/z, [%[inptr3], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z4.s\n" + "zip2 z11.s, z1.s, z4.s\n" + "zip1 z12.s, z2.s, z4.s\n" + "zip2 z13.s, z2.s, z4.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z4.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 5: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z5.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "ld1b z3.b, p0/z, [%[inptr3], %[inpos]]\n" + "ld1b z4.b, p0/z, [%[inptr4], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip2 z11.s, z1.s, z5.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z12.s, z2.s, z5.s\n" + "zip2 z13.s, z2.s, z5.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z5.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z5.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 6: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z6.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "ld1b z3.b, p0/z, [%[inptr3], %[inpos]]\n" + "ld1b z4.b, p0/z, [%[inptr4], %[inpos]]\n" + "ld1b z5.b, p0/z, [%[inptr5], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z6.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + case 7: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "mov z7.b, #0\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "ld1b z3.b, p0/z, [%[inptr3], %[inpos]]\n" + "ld1b z4.b, p0/z, [%[inptr4], %[inpos]]\n" + "ld1b z5.b, p0/z, [%[inptr5], %[inpos]]\n" + "ld1b z6.b, p0/z, [%[inptr6], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + default: + case 8: + __asm __volatile( + "1:\n" + "whilelt p0.b, %[inpos], %[inwidth]\n" + "b.none 2f\n" + "ld1b z0.b, p0/z, [%[inptr0], %[inpos]]\n" + "ld1b z1.b, p0/z, [%[inptr1], %[inpos]]\n" + "ld1b z2.b, p0/z, [%[inptr2], %[inpos]]\n" + "ld1b z3.b, p0/z, [%[inptr3], %[inpos]]\n" + "ld1b z4.b, p0/z, [%[inptr4], %[inpos]]\n" + "ld1b z5.b, p0/z, [%[inptr5], %[inpos]]\n" + "ld1b z6.b, p0/z, [%[inptr6], %[inpos]]\n" + "ld1b z7.b, p0/z, [%[inptr7], %[inpos]]\n" + "incb %[inpos], all, mul #1\n" + "zip1 z8.s, z0.s, z4.s\n" + "whilelt p0.b, %[outpos], %[outwidth]\n" + "zip2 z9.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "zip1 z12.s, z2.s, z6.s\n" + "zip2 z13.s, z2.s, z6.s\n" + "whilelt p1.b, %[outpos], %[outwidth]\n" + "zip1 z14.s, z3.s, z7.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z15.s, z3.s, z7.s\n" + "zip1 z0.s, z8.s, z12.s\n" + "zip2 z1.s, z8.s, z12.s\n" + "zip1 z2.s, z9.s, z13.s\n" + "whilelt p2.b, %[outpos], %[outwidth]\n" + "zip2 z3.s, z9.s, z13.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z4.s, z10.s, z14.s\n" + "zip2 z5.s, z10.s, z14.s\n" + "zip1 z6.s, z11.s, z15.s\n" + "zip2 z7.s, z11.s, z15.s\n" + "whilelt p3.b, %[outpos], %[outwidth]\n" + "zip1 z8.s, z0.s, z4.s\n" + "incb %[outpos], all, mul #1\n" + "zip2 z9.s, z0.s, z4.s\n" + "zip1 z10.s, z1.s, z5.s\n" + "zip2 z11.s, z1.s, z5.s\n" + "st1b z8.b, p0, [%[outptr]]\n" + "zip1 z12.s, z2.s, z6.s\n" + "whilelt p4.b, %[outpos], %[outwidth]\n" + "zip2 z13.s, z2.s, z6.s\n" + "incb %[outpos], all, mul #1\n" + "zip1 z14.s, z3.s, z7.s\n" + "st1b z9.b, p1, [%[outptr], #1, MUL VL]\n" + "zip2 z15.s, z3.s, z7.s\n" + "whilelt p5.b, %[outpos], %[outwidth]\n" + "st1b z10.b, p2, [%[outptr], #2, MUL VL]\n" + "incb %[outpos], all, mul #1\n" + "st1b z11.b, p3, [%[outptr], #3, MUL VL]\n" + "whilelt p6.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z12.b, p4, [%[outptr], #4, MUL VL]\n" + "whilelt p7.b, %[outpos], %[outwidth]\n" + "incb %[outpos], all, mul #1\n" + "st1b z13.b, p5, [%[outptr], #5, MUL VL]\n" + "st1b z14.b, p6, [%[outptr], #6, MUL VL]\n" + "st1b z15.b, p7, [%[outptr], #7, MUL VL]\n" + "addvl %[outptr], %[outptr], #8\n" + "b 1b\n" + "2:\n" + : [inpos] "+r" (inpos), [outpos] "+r" (outpos), [outptr] "+r" (outptr), [inptr0] "+r" (inptr0), [inptr1] "+r" (inptr1), [inptr2] "+r" (inptr2), [inptr3] "+r" (inptr3), [inptr4] "+r" (inptr4), [inptr5] "+r" (inptr5), [inptr6] "+r" (inptr6), [inptr7] "+r" (inptr7) + : [outwidth] "r" (outwidth), [inwidth] "r" (inwidth) + : "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "cc", "memory" + ); + break; + + + } + } +} + +#endif // __ARM_FEATURE_SVE |