diff options
author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-02 14:59:09 +0000 |
---|---|---|
committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-04 17:43:55 +0000 |
commit | cf87f509fc23d02c56569f794a3fb59e1b8be277 (patch) | |
tree | 0fe55158f2065dc6a314e82935558b9748165285 /src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp | |
parent | 89de118ccbebd5a943634137d0c160d4867da49c (diff) | |
download | ComputeLibrary-cf87f509fc23d02c56569f794a3fb59e1b8be277.tar.gz |
Tweak scheduling use of SQDMULH in quantized AVG pooling
Resolves COMPMID-4195
Change-Id: Ie5116c1ddddccafba40432fd4b5245bb27890a88
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4997
Reviewed-by: TeresaARM <teresa.charlinreyes@arm.com>
Reviewed-by: Manuel Bottini <manuel.bottini@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index bed484854b..ff8d7d8ba1 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -82,13 +82,12 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( __asm__ __volatile__( "ldr x4, [%x[args], %[offsetof_n_channels]]\n" "mov x5, #0x0\n" - "ldr x19, [%x[args], %[offsetof_outptrs]]\n" + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" "mov x6, #0x0\n" - "ldr q8, [%x[args], %[offsetof_rescale]]\n" - "ldp x7, x8, [x19, #0x0]\n" - "cmp x4, #0x4\n" - "ldp x17, x16, [x19, #0x10]\n" "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "cmp x4, #0x4\n" + "ldp x7, x8, [x20, #0x0]\n" + "ldp x17, x16, [x20, #0x10]\n" "ldp x15, x14, [x19, #0x0]\n" "ldp x13, x12, [x19, #0x10]\n" "ldp x11, x10, [x19, #0x20]\n" @@ -97,12 +96,14 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldp x25, x24, [x19, #0x50]\n" "ldp x23, x22, [x19, #0x60]\n" "ldp x21, x20, [x19, #0x70]\n" + "ldr q8, [%x[args], %[offsetof_rescale]]\n" "blt 3f\n" - "lsr x19, x4, #0x2\n" - "sub x4, x4, x19, LSL #2\n" "ldr q7, [x10, x5]\n" + "lsr x19, x4, #0x2\n" "ldr q6, [x9, x5]\n" + "sub x4, x4, x19, LSL #2\n" "ldr q5, [x26, x5]\n" + "subs x19, x19, #0x1\n" "ldr q4, [x25, x5]\n" "ldr q3, [x14, x5]\n" "ldr q2, [x13, x5]\n" @@ -117,26 +118,26 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldr q25, [x23, x5]\n" "ldr q24, [x20, x5]\n" "add x5, x5, #0x10\n" - "subs x19, x19, #0x1\n" "beq 2f\n" "1:" // Vector: Loop "fadd v17.4s, v7.4s, v6.4s\n" "ldr q7, [x10, x5]\n" + "subs x19, x19, #0x1\n" "fadd v16.4s, v5.4s, v4.4s\n" "ldr q6, [x9, x5]\n" "fadd v18.4s, v3.4s, v2.4s\n" "ldr q5, [x26, x5]\n" "fadd v23.4s, v1.4s, v0.4s\n" "ldr q4, [x25, x5]\n" - "fadd v17.4s, v17.4s, v16.4s\n" - "ldr q3, [x14, x5]\n" "fadd v22.4s, v31.4s, v30.4s\n" + "ldr q3, [x14, x5]\n" + "fadd v17.4s, v17.4s, v16.4s\n" "ldr q2, [x13, x5]\n" "fadd v16.4s, v29.4s, v28.4s\n" "ldr q1, [x11, x5]\n" - "fadd v21.4s, v18.4s, v17.4s\n" - "ldr q0, [x27, x5]\n" "fadd v19.4s, v27.4s, v23.4s\n" + "ldr q0, [x27, x5]\n" + "fadd v21.4s, v18.4s, v17.4s\n" "ldr q31, [x28, x5]\n" "fadd v20.4s, v16.4s, v17.4s\n" "ldr q30, [x24, x5]\n" @@ -146,21 +147,20 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldr q28, [x21, x5]\n" "fadd v16.4s, v24.4s, v22.4s\n" "ldr q27, [x15, x5]\n" - "fadd v19.4s, v19.4s, v21.4s\n" + "fadd v19.4s, v21.4s, v19.4s\n" "ldr q26, [x12, x5]\n" "fadd v18.4s, v21.4s, v18.4s\n" "ldr q25, [x23, x5]\n" "fadd v17.4s, v17.4s, v20.4s\n" "ldr q24, [x20, x5]\n" - "fadd v16.4s, v20.4s, v16.4s\n" "add x5, x5, #0x10\n" + "fadd v16.4s, v20.4s, v16.4s\n" "fmul v19.4s, v19.4s, v8.s[0]\n" - "subs x19, x19, #0x1\n" - "fmul v18.4s, v18.4s, v8.s[1]\n" "str q19, [x7, x6]\n" + "fmul v18.4s, v18.4s, v8.s[1]\n" "fmul v17.4s, v17.4s, v8.s[2]\n" - "fmul v16.4s, v16.4s, v8.s[3]\n" "str q18, [x8, x6]\n" + "fmul v16.4s, v16.4s, v8.s[3]\n" "str q17, [x17, x6]\n" "str q16, [x16, x6]\n" "add x6, x6, #0x10\n" @@ -179,7 +179,7 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "fadd v18.4s, v26.4s, v22.4s\n" "fadd v17.4s, v25.4s, v23.4s\n" "fadd v16.4s, v24.4s, v22.4s\n" - "fadd v19.4s, v19.4s, v21.4s\n" + "fadd v19.4s, v21.4s, v19.4s\n" "fadd v18.4s, v21.4s, v18.4s\n" "fadd v17.4s, v17.4s, v20.4s\n" "fadd v16.4s, v20.4s, v16.4s\n" @@ -195,6 +195,7 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "cbz x4, 4f\n" "3:" // Oddments "ldr s7, [x10, x5]\n" + "subs x4, x4, #0x1\n" "ldr s6, [x9, x5]\n" "fadd v17.4s, v7.4s, v6.4s\n" "ldr s5, [x26, x5]\n" @@ -207,33 +208,32 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( "ldr s0, [x27, x5]\n" "fadd v18.4s, v3.4s, v2.4s\n" "ldr s31, [x28, x5]\n" - "ldr s30, [x24, x5]\n" "fadd v23.4s, v1.4s, v0.4s\n" - "ldr s29, [x22, x5]\n" + "ldr s30, [x24, x5]\n" "fadd v21.4s, v18.4s, v17.4s\n" + "ldr s29, [x22, x5]\n" "ldr s28, [x21, x5]\n" - "ldr s27, [x15, x5]\n" "fadd v22.4s, v31.4s, v30.4s\n" + "ldr s27, [x15, x5]\n" "ldr s26, [x12, x5]\n" "fadd v16.4s, v29.4s, v28.4s\n" "ldr s25, [x23, x5]\n" - "fadd v19.4s, v27.4s, v23.4s\n" + "fadd v20.4s, v16.4s, v17.4s\n" "ldr s24, [x20, x5]\n" - "fadd v18.4s, v26.4s, v22.4s\n" "add x5, x5, #0x4\n" - "subs x4, x4, #0x1\n" - "fadd v20.4s, v16.4s, v17.4s\n" - "fadd v19.4s, v19.4s, v21.4s\n" - "fadd v18.4s, v21.4s, v18.4s\n" + "fadd v19.4s, v27.4s, v23.4s\n" + "fadd v18.4s, v26.4s, v22.4s\n" "fadd v17.4s, v25.4s, v23.4s\n" "fadd v16.4s, v24.4s, v22.4s\n" - "fmul v19.4s, v19.4s, v8.s[0]\n" - "str s19, [x7, x6]\n" + "fadd v19.4s, v21.4s, v19.4s\n" + "fadd v18.4s, v21.4s, v18.4s\n" "fadd v17.4s, v17.4s, v20.4s\n" "fadd v16.4s, v20.4s, v16.4s\n" + "fmul v19.4s, v19.4s, v8.s[0]\n" + "str s19, [x7, x6]\n" "fmul v18.4s, v18.4s, v8.s[1]\n" - "str s18, [x8, x6]\n" "fmul v17.4s, v17.4s, v8.s[2]\n" + "str s18, [x8, x6]\n" "fmul v16.4s, v16.4s, v8.s[3]\n" "str s17, [x17, x6]\n" "str s16, [x16, x6]\n" |