diff options
author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
---|---|---|
committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
commit | 74921eee924625426429044decefe3673561b174 (patch) | |
tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_conv/depthwise/interleaves | |
parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/interleaves')
8 files changed, 184 insertions, 388 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.cpp deleted file mode 100644 index d59d6b7e35..0000000000 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "8b_mla.hpp" - -size_t generic_get_packed_size( - const VLType vec_type, - const unsigned int acc_depth, - const unsigned int kernel_rows, - const unsigned int kernel_cols, - const unsigned int n_input_channels -) -{ - const auto per_iter = acc_depth * arm_gemm::utils::get_vector_length<int32_t>(vec_type); - return arm_gemm::roundup((long unsigned int) n_input_channels, per_iter) * kernel_rows * kernel_cols * sizeof(int8_t); -} - -void generic_pack( - const VLType vec_type, - const unsigned int acc_depth, - const unsigned int kernel_rows, - const unsigned int kernel_cols, - const unsigned int n_channels, - void *_outptr, - const void *_weights, - size_t ld_weight_col, - size_t ld_weight_row -) -{ - int8_t *outptr = reinterpret_cast<int8_t *>(_outptr); - const int8_t *weights = reinterpret_cast<const int8_t *>(_weights); - - // Get the strides - ld_weight_col = (ld_weight_col == 0) ? n_channels * sizeof(int8_t) : ld_weight_col; - ld_weight_row = (ld_weight_row == 0) ? kernel_cols * ld_weight_col : ld_weight_row; - - // Pack into per-iter chunks. - const auto per_iter = acc_depth * arm_gemm::utils::get_vector_length<int32_t>(vec_type); - for (unsigned int c = 0; c < n_channels; c += per_iter) - { - auto weight_row = weights + c; - const auto to_copy = std::min<unsigned int>(per_iter, n_channels - c); - - for (unsigned int i = 0; i < kernel_rows; i++) - { - auto weight_col = weight_row; - - for (unsigned int j = 0; j < kernel_cols; j++) - { - memcpy(outptr, weight_col, to_copy); - outptr += per_iter; - weight_col += ld_weight_col; - } - - weight_row += ld_weight_row; - } - } -} - -namespace arm_conv { -namespace depthwise { - -ADD_IMPLEMENTATION(a64, s8q, int8_t, None, 2, 3, 3) -ADD_IMPLEMENTATION(a64, s8q, int8_t, None, 2, 5, 5) -ADD_IMPLEMENTATION(a64, u8q, uint8_t, None, 2, 3, 3) -ADD_IMPLEMENTATION(a64, u8q, uint8_t, None, 2, 5, 5) - -} // namespace depthwise -} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.hpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.hpp deleted file mode 100644 index 3176d1dedd..0000000000 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/8b_mla.hpp +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "arm_gemm.hpp" -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" -#include "src/core/NEON/kernels/assembly/depthwise.hpp" -#include <cstdint> -#include <cstring> - -using namespace arm_gemm; - -size_t generic_get_packed_size( - const VLType vec_type, - const unsigned int acc_depth, - const unsigned int kernel_rows, - const unsigned int kernel_cols, - const unsigned int n_input_channels -); - -void generic_pack( - const VLType vec_type, - const unsigned int acc_depth, - const unsigned int kernel_rows, - const unsigned int kernel_cols, - const unsigned int n_channels, - void *_outptr, - const void *_weights, - size_t ld_weight_col, - size_t ld_weight_row -); - -#define ADD_IMPLEMENTATION(ARCH, TYPENAME, TYPE, VEC_TYPE, ACC_DEPTH, KERN_ROWS, KERN_COLS) \ -struct interleave_ ## ARCH ## _ ## TYPENAME ## _ ## KERN_ROWS ## x ## KERN_COLS ## _mla \ -{ \ - static size_t get_packed_size(const DepthwiseArgs &args); \ - static void pack_parameters( \ - unsigned int n_channels, void *outptr, \ - const TYPE *weights, size_t ld_weight_col, size_t ld_weight_row \ - ); \ -}; \ -\ -size_t interleave_ ## ARCH ## _ ## TYPENAME ## _ ## KERN_ROWS ## x ## KERN_COLS ## _mla::get_packed_size(const DepthwiseArgs &args) \ -{ \ - return generic_get_packed_size(VLType::VEC_TYPE, ACC_DEPTH, KERN_ROWS, KERN_COLS, args.input_channels); \ -} \ -\ -void interleave_ ## ARCH ## _ ## TYPENAME ## _ ## KERN_ROWS ## x ## KERN_COLS ## _mla::pack_parameters(unsigned int n_channels, void *outptr, \ - const TYPE *weights, size_t ld_weight_col, size_t ld_weight_row) \ -{ \ - generic_pack(VLType::VEC_TYPE, ACC_DEPTH, KERN_ROWS, KERN_COLS, n_channels, outptr, weights, ld_weight_col, ld_weight_row); \ -} diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_s8q_3x3_dot.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_s8q_3x3_dot.cpp index adda78f164..5e4bf99120 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_s8q_3x3_dot.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_s8q_3x3_dot.cpp @@ -25,8 +25,8 @@ #if defined(__aarch64__) #include "arm_gemm.hpp" -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" -#include "src/core/NEON/kernels/assembly/depthwise.hpp" +#include "utils.hpp" +#include "depthwise.hpp" #include <cstdint> namespace arm_conv { @@ -54,162 +54,162 @@ void interleave_a64_s8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "cmp %x[ld_weight_col], XZR\n" "csel %x[ld_weight_col], %x[ld_weight_col], %x[n_channels], NE\n" "movi v16.4s, #0x9\n" - "movi v0.16b, #0x0\n" + "movi v31.16b, #0x0\n" "mov x21, #0x3\n" "mul x21, %x[ld_weight_col], x21\n" "add x20, %x[qp], %[offsetof_input_offset]\n" - "ld1r { v31.4s }, [x20]\n" - "add x20, %x[qp], %[offsetof_weights_offset]\n" "ld1r { v30.4s }, [x20]\n" + "add x20, %x[qp], %[offsetof_weights_offset]\n" + "ld1r { v29.4s }, [x20]\n" "cmp %x[ld_weight_row], XZR\n" - "mul v30.4s, v30.4s, v31.4s\n" + "mul v29.4s, v29.4s, v30.4s\n" "csel %x[ld_weight_row], %x[ld_weight_row], x21, NE\n" "lsr x21, %x[n_channels], #0x2\n" - "movi v29.16b, #0x1\n" - "mul v30.4s, v30.4s, v16.4s\n" + "movi v28.16b, #0x1\n" + "mul v29.4s, v29.4s, v16.4s\n" "add x25, %x[weights], %x[ld_weight_row]\n" "add x20, %x[qp], %[offsetof_per_layer_mul]\n" - "ld1r { v28.4s }, [x20]\n" - "add x20, %x[qp], %[offsetof_per_layer_right_shift]\n" "ld1r { v27.4s }, [x20]\n" + "add x20, %x[qp], %[offsetof_per_layer_right_shift]\n" + "ld1r { v26.4s }, [x20]\n" "add x24, x25, %x[ld_weight_row]\n" "add x23, %x[ld_weight_col], %x[ld_weight_col]\n" "mov x22, #0x0\n" "cbz x21, 4f\n" "1:" // Loop - "movi v26.4s, #0x0\n" + "movi v25.4s, #0x0\n" "cbz %x[bias], 2f\n" - "ldr q26, [%x[bias], x22]\n" + "ldr q25, [%x[bias], x22]\n" "2:" // Loop: Skip bias load - "ldr s25, [%x[weights], #0x0]\n" - "ldr s22, [%x[weights], %x[ld_weight_col]]\n" - "zip1 v22.16b, v22.16b, v0.16b\n" - "movi v24.4s, #0x0\n" - "ldr s20, [%x[weights], x23]\n" - "ldr s23, [x25, #0x0]\n" - "zip1 v20.16b, v25.16b, v20.16b\n" - "zip1 v22.16b, v20.16b, v22.16b\n" - "ldr s21, [x25, %x[ld_weight_col]]\n" - "ldr s18, [x25, x23]\n" - "zip1 v20.16b, v23.16b, v18.16b\n" - "zip1 v18.16b, v21.16b, v0.16b\n" + "ldr s19, [%x[weights], #0x0]\n" + "ldr s16, [%x[weights], %x[ld_weight_col]]\n" + "zip1 v17.16b, v16.16b, v31.16b\n" + "movi v21.4s, #0x0\n" + "ldr s16, [%x[weights], x23]\n" + "ldr s18, [x25, #0x0]\n" + "zip1 v16.16b, v19.16b, v16.16b\n" + "zip1 v20.16b, v16.16b, v17.16b\n" + "ldr s17, [x25, %x[ld_weight_col]]\n" + "ldr s16, [x25, x23]\n" + "zip1 v18.16b, v18.16b, v16.16b\n" + "zip1 v16.16b, v17.16b, v31.16b\n" "ldr s17, [x24, #0x0]\n" "ldr s19, [x24, %x[ld_weight_col]]\n" - ".inst 0x4e9697b8 // sdot v24.4s, v29.16b, v22.16b\n" - "zip1 v18.16b, v20.16b, v18.16b\n" + ".inst 0x4e949795 // sdot v21.4s, v28.16b, v20.16b\n" + "zip1 v18.16b, v18.16b, v16.16b\n" "ldr s16, [x24, x23]\n" "zip1 v17.16b, v17.16b, v16.16b\n" - "zip1 v16.16b, v19.16b, v0.16b\n" - ".inst 0x4e9297b8 // sdot v24.4s, v29.16b, v18.16b\n" + "zip1 v16.16b, v19.16b, v31.16b\n" + ".inst 0x4e929795 // sdot v21.4s, v28.16b, v18.16b\n" "zip1 v16.16b, v17.16b, v16.16b\n" - ".inst 0x4e9097b8 // sdot v24.4s, v29.16b, v16.16b\n" + ".inst 0x4e909795 // sdot v21.4s, v28.16b, v16.16b\n" "add %x[weights], %x[weights], #0x4\n" "add x25, x25, #0x4\n" - "mls v26.4s, v24.4s, v31.4s\n" + "mls v25.4s, v21.4s, v30.4s\n" "add x24, x24, #0x4\n" - "add v26.4s, v26.4s, v30.4s\n" - "str q26, [%x[outptr], #0x0]\n" - "str q22, [%x[outptr], #0x10]\n" + "add v25.4s, v25.4s, v29.4s\n" + "str q25, [%x[outptr], #0x0]\n" + "str q20, [%x[outptr], #0x10]\n" "str q18, [%x[outptr], #0x20]\n" "str q16, [%x[outptr], #0x30]\n" "add %x[outptr], %x[outptr], #0x40\n" "cbz %x[rq_mul_perchannel], 3f\n" - "ldr q28, [%x[rq_mul_perchannel], x22]\n" - "ldr q27, [%x[rq_shift_perchannel], x22]\n" + "ldr q27, [%x[rq_mul_perchannel], x22]\n" + "ldr q26, [%x[rq_shift_perchannel], x22]\n" "3:" // Loop: Quantisation parameters: Store "subs x21, x21, #0x1\n" - "str q28, [%x[outptr], #0x0]\n" + "str q27, [%x[outptr], #0x0]\n" "add x22, x22, #0x10\n" - "str q27, [%x[outptr], #0x10]\n" + "str q26, [%x[outptr], #0x10]\n" "add %x[outptr], %x[outptr], #0x20\n" "bgt 1b\n" "tst %x[n_channels], #0x3\n" "beq 13f\n" "4:" // Oddments - "movi v26.4s, #0x0\n" + "movi v25.4s, #0x0\n" "cbz %x[bias], 7f\n" "add %x[bias], %x[bias], x22\n" "tbz %x[n_channels], #1, 5f\n" - "ld1 { v26.d }[0], [%x[bias]], #0x8\n" + "ld1 { v25.d }[0], [%x[bias]], #0x8\n" "tbz %x[n_channels], #0, 6f\n" - "ld1 { v26.s }[2], [%x[bias]], #0x4\n" + "ld1 { v25.s }[2], [%x[bias]], #0x4\n" "b 6f\n" "5:" // Oddments: Load bias: Bit 1: Unset - "ld1 { v26.s }[0], [%x[bias]], #0x4\n" + "ld1 { v25.s }[0], [%x[bias]], #0x4\n" "6:" // Oddments: Load bias: Bit 1: End "7:" // Oddments: Skip bias load "tbz %x[n_channels], #1, 8f\n" - "ld1 { v25.h }[0], [%x[weights]]\n" - "ld1 { v23.h }[0], [x25]\n" + "ld1 { v17.h }[0], [%x[weights]]\n" + "ld1 { v24.h }[0], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.h }[0], [x21]\n" - "ld1 { v20.h }[0], [x20]\n" + "ld1 { v20.h }[0], [x21]\n" + "ld1 { v16.h }[0], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.h }[0], [x21]\n" + "ld1 { v19.h }[0], [x21]\n" "ld1 { v18.h }[0], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.h }[0], [x24]\n" - "ld1 { v19.h }[0], [x21]\n" + "ld1 { v23.h }[0], [x24]\n" + "ld1 { v22.h }[0], [x21]\n" "add %x[weights], %x[weights], #0x2\n" "add x25, x25, #0x2\n" - "ld1 { v16.h }[0], [x20]\n" + "ld1 { v21.h }[0], [x20]\n" "add x24, x24, #0x2\n" "tbz %x[n_channels], #0, 9f\n" - "ld1 { v25.b }[2], [%x[weights]]\n" - "ld1 { v23.b }[2], [x25]\n" + "ld1 { v17.b }[2], [%x[weights]]\n" + "ld1 { v24.b }[2], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.b }[2], [x21]\n" - "ld1 { v20.b }[2], [x20]\n" + "ld1 { v20.b }[2], [x21]\n" + "ld1 { v16.b }[2], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.b }[2], [x21]\n" + "ld1 { v19.b }[2], [x21]\n" "ld1 { v18.b }[2], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.b }[2], [x24]\n" - "ld1 { v19.b }[2], [x21]\n" + "ld1 { v23.b }[2], [x24]\n" + "ld1 { v22.b }[2], [x21]\n" "add %x[weights], %x[weights], #0x1\n" - "ld1 { v16.b }[2], [x20]\n" + "ld1 { v21.b }[2], [x20]\n" "b 9f\n" "8:" // Oddments: Load weights: Bit 1: Unset - "ld1 { v25.b }[0], [%x[weights]]\n" - "ld1 { v23.b }[0], [x25]\n" + "ld1 { v17.b }[0], [%x[weights]]\n" + "ld1 { v24.b }[0], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.b }[0], [x21]\n" - "ld1 { v20.b }[0], [x20]\n" + "ld1 { v20.b }[0], [x21]\n" + "ld1 { v16.b }[0], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.b }[0], [x21]\n" + "ld1 { v19.b }[0], [x21]\n" "ld1 { v18.b }[0], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.b }[0], [x24]\n" - "ld1 { v19.b }[0], [x21]\n" + "ld1 { v23.b }[0], [x24]\n" + "ld1 { v22.b }[0], [x21]\n" "add %x[weights], %x[weights], #0x1\n" - "ld1 { v16.b }[0], [x20]\n" + "ld1 { v21.b }[0], [x20]\n" "9:" // Oddments: Load weights: Bit 1: End - "zip1 v20.16b, v25.16b, v20.16b\n" - "zip1 v22.16b, v22.16b, v0.16b\n" - "zip1 v22.16b, v20.16b, v22.16b\n" - "zip1 v20.16b, v23.16b, v18.16b\n" - "zip1 v18.16b, v21.16b, v0.16b\n" - "movi v24.4s, #0x0\n" - ".inst 0x4e9697b8 // sdot v24.4s, v29.16b, v22.16b\n" - "zip1 v18.16b, v20.16b, v18.16b\n" "zip1 v17.16b, v17.16b, v16.16b\n" - ".inst 0x4e9297b8 // sdot v24.4s, v29.16b, v18.16b\n" - "zip1 v16.16b, v19.16b, v0.16b\n" + "zip1 v16.16b, v20.16b, v31.16b\n" + "zip1 v20.16b, v17.16b, v16.16b\n" + "zip1 v17.16b, v24.16b, v18.16b\n" + "zip1 v16.16b, v19.16b, v31.16b\n" + "movi v19.4s, #0x0\n" + ".inst 0x4e949793 // sdot v19.4s, v28.16b, v20.16b\n" + "zip1 v18.16b, v17.16b, v16.16b\n" + "zip1 v17.16b, v23.16b, v21.16b\n" + ".inst 0x4e929793 // sdot v19.4s, v28.16b, v18.16b\n" + "zip1 v16.16b, v22.16b, v31.16b\n" "zip1 v16.16b, v17.16b, v16.16b\n" - ".inst 0x4e9097b8 // sdot v24.4s, v29.16b, v16.16b\n" - "mls v26.4s, v24.4s, v31.4s\n" - "add v26.4s, v26.4s, v30.4s\n" - "str q26, [%x[outptr], #0x0]\n" - "str q22, [%x[outptr], #0x10]\n" + ".inst 0x4e909793 // sdot v19.4s, v28.16b, v16.16b\n" + "mls v25.4s, v19.4s, v30.4s\n" + "add v25.4s, v25.4s, v29.4s\n" + "str q25, [%x[outptr], #0x0]\n" + "str q20, [%x[outptr], #0x10]\n" "str q18, [%x[outptr], #0x20]\n" "str q16, [%x[outptr], #0x30]\n" "add %x[outptr], %x[outptr], #0x40\n" @@ -217,24 +217,24 @@ void interleave_a64_s8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "add x21, %x[rq_mul_perchannel], x22\n" "add x20, %x[rq_shift_perchannel], x22\n" "tbz %x[n_channels], #1, 10f\n" - "ld1 { v28.d }[0], [x21], #0x8\n" - "ld1 { v27.d }[0], [x20], #0x8\n" + "ld1 { v27.d }[0], [x21], #0x8\n" + "ld1 { v26.d }[0], [x20], #0x8\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v28.s }[2], [x21], #0x4\n" - "ld1 { v27.s }[2], [x20], #0x4\n" + "ld1 { v27.s }[2], [x21], #0x4\n" + "ld1 { v26.s }[2], [x20], #0x4\n" "b 11f\n" "10:" // Oddments: Quantisation parameters: Load quant params: Bit 1: Unset - "ld1 { v28.s }[0], [x21], #0x4\n" - "ld1 { v27.s }[0], [x20], #0x4\n" + "ld1 { v27.s }[0], [x21], #0x4\n" + "ld1 { v26.s }[0], [x20], #0x4\n" "11:" // Oddments: Quantisation parameters: Load quant params: Bit 1: End "12:" // Oddments: Quantisation parameters: Store - "str q28, [%x[outptr], #0x0]\n" - "str q27, [%x[outptr], #0x10]\n" + "str q27, [%x[outptr], #0x0]\n" + "str q26, [%x[outptr], #0x10]\n" "add %x[outptr], %x[outptr], #0x20\n" "13:" // End : [bias] "+&r" (bias), [ld_weight_col] "+&r" (ld_weight_col), [ld_weight_row] "+&r" (ld_weight_row), [outptr] "+&r" (outptr), [weights] "+&r" (weights) : [n_channels] "r" (n_channels), [offsetof_input_offset] "I" (offsetof(arm_gemm::Requantize32, a_offset)), [offsetof_per_layer_mul] "I" (offsetof(arm_gemm::Requantize32, per_layer_mul)), [offsetof_per_layer_right_shift] "I" (offsetof(arm_gemm::Requantize32, per_layer_right_shift)), [offsetof_weights_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [qp] "r" (&qp), [rq_mul_perchannel] "r" (qp.per_channel_muls), [rq_shift_perchannel] "r" (qp.per_channel_right_shifts) - : "cc", "memory", "v0", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25" ); } diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_u8q_3x3_dot.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_u8q_3x3_dot.cpp index b89886ae0c..314f09a0c5 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_u8q_3x3_dot.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/a64_u8q_3x3_dot.cpp @@ -25,8 +25,8 @@ #if defined(__aarch64__) #include "arm_gemm.hpp" -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" -#include "src/core/NEON/kernels/assembly/depthwise.hpp" +#include "utils.hpp" +#include "depthwise.hpp" #include <cstdint> namespace arm_conv { @@ -54,162 +54,162 @@ void interleave_a64_u8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "cmp %x[ld_weight_col], XZR\n" "csel %x[ld_weight_col], %x[ld_weight_col], %x[n_channels], NE\n" "movi v16.4s, #0x9\n" - "movi v0.16b, #0x0\n" + "movi v31.16b, #0x0\n" "mov x21, #0x3\n" "mul x21, %x[ld_weight_col], x21\n" "add x20, %x[qp], %[offsetof_input_offset]\n" - "ld1r { v31.4s }, [x20]\n" - "add x20, %x[qp], %[offsetof_weights_offset]\n" "ld1r { v30.4s }, [x20]\n" + "add x20, %x[qp], %[offsetof_weights_offset]\n" + "ld1r { v29.4s }, [x20]\n" "cmp %x[ld_weight_row], XZR\n" - "mul v30.4s, v30.4s, v31.4s\n" + "mul v29.4s, v29.4s, v30.4s\n" "csel %x[ld_weight_row], %x[ld_weight_row], x21, NE\n" "lsr x21, %x[n_channels], #0x2\n" - "movi v29.16b, #0x1\n" - "mul v30.4s, v30.4s, v16.4s\n" + "movi v28.16b, #0x1\n" + "mul v29.4s, v29.4s, v16.4s\n" "add x25, %x[weights], %x[ld_weight_row]\n" "add x20, %x[qp], %[offsetof_per_layer_mul]\n" - "ld1r { v28.4s }, [x20]\n" - "add x20, %x[qp], %[offsetof_per_layer_right_shift]\n" "ld1r { v27.4s }, [x20]\n" + "add x20, %x[qp], %[offsetof_per_layer_right_shift]\n" + "ld1r { v26.4s }, [x20]\n" "add x24, x25, %x[ld_weight_row]\n" "add x23, %x[ld_weight_col], %x[ld_weight_col]\n" "mov x22, #0x0\n" "cbz x21, 4f\n" "1:" // Loop - "movi v26.4s, #0x0\n" + "movi v25.4s, #0x0\n" "cbz %x[bias], 2f\n" - "ldr q26, [%x[bias], x22]\n" + "ldr q25, [%x[bias], x22]\n" "2:" // Loop: Skip bias load - "ldr s25, [%x[weights], #0x0]\n" - "ldr s22, [%x[weights], %x[ld_weight_col]]\n" - "zip1 v22.16b, v22.16b, v0.16b\n" - "movi v24.4s, #0x0\n" - "ldr s20, [%x[weights], x23]\n" - "ldr s23, [x25, #0x0]\n" - "zip1 v20.16b, v25.16b, v20.16b\n" - "zip1 v22.16b, v20.16b, v22.16b\n" - "ldr s21, [x25, %x[ld_weight_col]]\n" - "ldr s18, [x25, x23]\n" - "zip1 v20.16b, v23.16b, v18.16b\n" - "zip1 v18.16b, v21.16b, v0.16b\n" + "ldr s19, [%x[weights], #0x0]\n" + "ldr s16, [%x[weights], %x[ld_weight_col]]\n" + "zip1 v17.16b, v16.16b, v31.16b\n" + "movi v21.4s, #0x0\n" + "ldr s16, [%x[weights], x23]\n" + "ldr s18, [x25, #0x0]\n" + "zip1 v16.16b, v19.16b, v16.16b\n" + "zip1 v20.16b, v16.16b, v17.16b\n" + "ldr s17, [x25, %x[ld_weight_col]]\n" + "ldr s16, [x25, x23]\n" + "zip1 v18.16b, v18.16b, v16.16b\n" + "zip1 v16.16b, v17.16b, v31.16b\n" "ldr s17, [x24, #0x0]\n" "ldr s19, [x24, %x[ld_weight_col]]\n" - ".inst 0x6e9697b8 // udot v24.4s, v29.16b, v22.16b\n" - "zip1 v18.16b, v20.16b, v18.16b\n" + ".inst 0x6e949795 // udot v21.4s, v28.16b, v20.16b\n" + "zip1 v18.16b, v18.16b, v16.16b\n" "ldr s16, [x24, x23]\n" "zip1 v17.16b, v17.16b, v16.16b\n" - "zip1 v16.16b, v19.16b, v0.16b\n" - ".inst 0x6e9297b8 // udot v24.4s, v29.16b, v18.16b\n" + "zip1 v16.16b, v19.16b, v31.16b\n" + ".inst 0x6e929795 // udot v21.4s, v28.16b, v18.16b\n" "zip1 v16.16b, v17.16b, v16.16b\n" - ".inst 0x6e9097b8 // udot v24.4s, v29.16b, v16.16b\n" + ".inst 0x6e909795 // udot v21.4s, v28.16b, v16.16b\n" "add %x[weights], %x[weights], #0x4\n" "add x25, x25, #0x4\n" - "mls v26.4s, v24.4s, v31.4s\n" + "mls v25.4s, v21.4s, v30.4s\n" "add x24, x24, #0x4\n" - "add v26.4s, v26.4s, v30.4s\n" - "str q26, [%x[outptr], #0x0]\n" - "str q22, [%x[outptr], #0x10]\n" + "add v25.4s, v25.4s, v29.4s\n" + "str q25, [%x[outptr], #0x0]\n" + "str q20, [%x[outptr], #0x10]\n" "str q18, [%x[outptr], #0x20]\n" "str q16, [%x[outptr], #0x30]\n" "add %x[outptr], %x[outptr], #0x40\n" "cbz %x[rq_mul_perchannel], 3f\n" - "ldr q28, [%x[rq_mul_perchannel], x22]\n" - "ldr q27, [%x[rq_shift_perchannel], x22]\n" + "ldr q27, [%x[rq_mul_perchannel], x22]\n" + "ldr q26, [%x[rq_shift_perchannel], x22]\n" "3:" // Loop: Quantisation parameters: Store "subs x21, x21, #0x1\n" - "str q28, [%x[outptr], #0x0]\n" + "str q27, [%x[outptr], #0x0]\n" "add x22, x22, #0x10\n" - "str q27, [%x[outptr], #0x10]\n" + "str q26, [%x[outptr], #0x10]\n" "add %x[outptr], %x[outptr], #0x20\n" "bgt 1b\n" "tst %x[n_channels], #0x3\n" "beq 13f\n" "4:" // Oddments - "movi v26.4s, #0x0\n" + "movi v25.4s, #0x0\n" "cbz %x[bias], 7f\n" "add %x[bias], %x[bias], x22\n" "tbz %x[n_channels], #1, 5f\n" - "ld1 { v26.d }[0], [%x[bias]], #0x8\n" + "ld1 { v25.d }[0], [%x[bias]], #0x8\n" "tbz %x[n_channels], #0, 6f\n" - "ld1 { v26.s }[2], [%x[bias]], #0x4\n" + "ld1 { v25.s }[2], [%x[bias]], #0x4\n" "b 6f\n" "5:" // Oddments: Load bias: Bit 1: Unset - "ld1 { v26.s }[0], [%x[bias]], #0x4\n" + "ld1 { v25.s }[0], [%x[bias]], #0x4\n" "6:" // Oddments: Load bias: Bit 1: End "7:" // Oddments: Skip bias load "tbz %x[n_channels], #1, 8f\n" - "ld1 { v25.h }[0], [%x[weights]]\n" - "ld1 { v23.h }[0], [x25]\n" + "ld1 { v17.h }[0], [%x[weights]]\n" + "ld1 { v24.h }[0], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.h }[0], [x21]\n" - "ld1 { v20.h }[0], [x20]\n" + "ld1 { v20.h }[0], [x21]\n" + "ld1 { v16.h }[0], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.h }[0], [x21]\n" + "ld1 { v19.h }[0], [x21]\n" "ld1 { v18.h }[0], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.h }[0], [x24]\n" - "ld1 { v19.h }[0], [x21]\n" + "ld1 { v23.h }[0], [x24]\n" + "ld1 { v22.h }[0], [x21]\n" "add %x[weights], %x[weights], #0x2\n" "add x25, x25, #0x2\n" - "ld1 { v16.h }[0], [x20]\n" + "ld1 { v21.h }[0], [x20]\n" "add x24, x24, #0x2\n" "tbz %x[n_channels], #0, 9f\n" - "ld1 { v25.b }[2], [%x[weights]]\n" - "ld1 { v23.b }[2], [x25]\n" + "ld1 { v17.b }[2], [%x[weights]]\n" + "ld1 { v24.b }[2], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.b }[2], [x21]\n" - "ld1 { v20.b }[2], [x20]\n" + "ld1 { v20.b }[2], [x21]\n" + "ld1 { v16.b }[2], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.b }[2], [x21]\n" + "ld1 { v19.b }[2], [x21]\n" "ld1 { v18.b }[2], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.b }[2], [x24]\n" - "ld1 { v19.b }[2], [x21]\n" + "ld1 { v23.b }[2], [x24]\n" + "ld1 { v22.b }[2], [x21]\n" "add %x[weights], %x[weights], #0x1\n" - "ld1 { v16.b }[2], [x20]\n" + "ld1 { v21.b }[2], [x20]\n" "b 9f\n" "8:" // Oddments: Load weights: Bit 1: Unset - "ld1 { v25.b }[0], [%x[weights]]\n" - "ld1 { v23.b }[0], [x25]\n" + "ld1 { v17.b }[0], [%x[weights]]\n" + "ld1 { v24.b }[0], [x25]\n" "add x21, %x[weights], %x[ld_weight_col]\n" "add x20, %x[weights], x23\n" - "ld1 { v22.b }[0], [x21]\n" - "ld1 { v20.b }[0], [x20]\n" + "ld1 { v20.b }[0], [x21]\n" + "ld1 { v16.b }[0], [x20]\n" "add x21, x25, %x[ld_weight_col]\n" "add x20, x25, x23\n" - "ld1 { v21.b }[0], [x21]\n" + "ld1 { v19.b }[0], [x21]\n" "ld1 { v18.b }[0], [x20]\n" "add x21, x24, %x[ld_weight_col]\n" "add x20, x24, x23\n" - "ld1 { v17.b }[0], [x24]\n" - "ld1 { v19.b }[0], [x21]\n" + "ld1 { v23.b }[0], [x24]\n" + "ld1 { v22.b }[0], [x21]\n" "add %x[weights], %x[weights], #0x1\n" - "ld1 { v16.b }[0], [x20]\n" + "ld1 { v21.b }[0], [x20]\n" "9:" // Oddments: Load weights: Bit 1: End - "zip1 v20.16b, v25.16b, v20.16b\n" - "zip1 v22.16b, v22.16b, v0.16b\n" - "zip1 v22.16b, v20.16b, v22.16b\n" - "zip1 v20.16b, v23.16b, v18.16b\n" - "zip1 v18.16b, v21.16b, v0.16b\n" - "movi v24.4s, #0x0\n" - ".inst 0x6e9697b8 // udot v24.4s, v29.16b, v22.16b\n" - "zip1 v18.16b, v20.16b, v18.16b\n" "zip1 v17.16b, v17.16b, v16.16b\n" - ".inst 0x6e9297b8 // udot v24.4s, v29.16b, v18.16b\n" - "zip1 v16.16b, v19.16b, v0.16b\n" + "zip1 v16.16b, v20.16b, v31.16b\n" + "zip1 v20.16b, v17.16b, v16.16b\n" + "zip1 v17.16b, v24.16b, v18.16b\n" + "zip1 v16.16b, v19.16b, v31.16b\n" + "movi v19.4s, #0x0\n" + ".inst 0x6e949793 // udot v19.4s, v28.16b, v20.16b\n" + "zip1 v18.16b, v17.16b, v16.16b\n" + "zip1 v17.16b, v23.16b, v21.16b\n" + ".inst 0x6e929793 // udot v19.4s, v28.16b, v18.16b\n" + "zip1 v16.16b, v22.16b, v31.16b\n" "zip1 v16.16b, v17.16b, v16.16b\n" - ".inst 0x6e9097b8 // udot v24.4s, v29.16b, v16.16b\n" - "mls v26.4s, v24.4s, v31.4s\n" - "add v26.4s, v26.4s, v30.4s\n" - "str q26, [%x[outptr], #0x0]\n" - "str q22, [%x[outptr], #0x10]\n" + ".inst 0x6e909793 // udot v19.4s, v28.16b, v16.16b\n" + "mls v25.4s, v19.4s, v30.4s\n" + "add v25.4s, v25.4s, v29.4s\n" + "str q25, [%x[outptr], #0x0]\n" + "str q20, [%x[outptr], #0x10]\n" "str q18, [%x[outptr], #0x20]\n" "str q16, [%x[outptr], #0x30]\n" "add %x[outptr], %x[outptr], #0x40\n" @@ -217,24 +217,24 @@ void interleave_a64_u8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "add x21, %x[rq_mul_perchannel], x22\n" "add x20, %x[rq_shift_perchannel], x22\n" "tbz %x[n_channels], #1, 10f\n" - "ld1 { v28.d }[0], [x21], #0x8\n" - "ld1 { v27.d }[0], [x20], #0x8\n" + "ld1 { v27.d }[0], [x21], #0x8\n" + "ld1 { v26.d }[0], [x20], #0x8\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v28.s }[2], [x21], #0x4\n" - "ld1 { v27.s }[2], [x20], #0x4\n" + "ld1 { v27.s }[2], [x21], #0x4\n" + "ld1 { v26.s }[2], [x20], #0x4\n" "b 11f\n" "10:" // Oddments: Quantisation parameters: Load quant params: Bit 1: Unset - "ld1 { v28.s }[0], [x21], #0x4\n" - "ld1 { v27.s }[0], [x20], #0x4\n" + "ld1 { v27.s }[0], [x21], #0x4\n" + "ld1 { v26.s }[0], [x20], #0x4\n" "11:" // Oddments: Quantisation parameters: Load quant params: Bit 1: End "12:" // Oddments: Quantisation parameters: Store - "str q28, [%x[outptr], #0x0]\n" - "str q27, [%x[outptr], #0x10]\n" + "str q27, [%x[outptr], #0x0]\n" + "str q26, [%x[outptr], #0x10]\n" "add %x[outptr], %x[outptr], #0x20\n" "13:" // End : [bias] "+&r" (bias), [ld_weight_col] "+&r" (ld_weight_col), [ld_weight_row] "+&r" (ld_weight_row), [outptr] "+&r" (outptr), [weights] "+&r" (weights) : [n_channels] "r" (n_channels), [offsetof_input_offset] "I" (offsetof(arm_gemm::Requantize32, a_offset)), [offsetof_per_layer_mul] "I" (offsetof(arm_gemm::Requantize32, per_layer_mul)), [offsetof_per_layer_right_shift] "I" (offsetof(arm_gemm::Requantize32, per_layer_right_shift)), [offsetof_weights_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [qp] "r" (&qp), [rq_mul_perchannel] "r" (qp.per_channel_muls), [rq_shift_perchannel] "r" (qp.per_channel_right_shifts) - : "cc", "memory", "v0", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25" ); } diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/generic.hpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/generic.hpp index 5b5ae17806..756c50b98c 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/generic.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/generic.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,7 +24,7 @@ #pragma once -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" +#include "utils.hpp" #include "depthwise.hpp" #include <functional> diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_8b_mla.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_8b_mla.cpp deleted file mode 100644 index de74ca5f43..0000000000 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_8b_mla.cpp +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "8b_mla.hpp" - -namespace arm_conv { -namespace depthwise { - -#if defined(__ARM_FEATURE_SVE) - -ADD_IMPLEMENTATION(sve, s8q, int8_t, SVE, 2, 3, 3) -ADD_IMPLEMENTATION(sve, s8q, int8_t, SVE, 2, 5, 5) -ADD_IMPLEMENTATION(sve, u8q, uint8_t, SVE, 2, 3, 3) -ADD_IMPLEMENTATION(sve, u8q, uint8_t, SVE, 2, 5, 5) - -#endif // defined(__ARM_FEATURE_SVE) - -} // namespace depthwise -} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_s8q_3x3_dot.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_s8q_3x3_dot.cpp index 0cf8044733..3a4999296a 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_s8q_3x3_dot.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_s8q_3x3_dot.cpp @@ -25,8 +25,8 @@ #if defined(ARM_COMPUTE_ENABLE_SVE) #include "arm_gemm.hpp" -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" -#include "src/core/NEON/kernels/assembly/depthwise.hpp" +#include "utils.hpp" +#include "depthwise.hpp" #include <cstdint> namespace arm_conv { @@ -76,7 +76,6 @@ void interleave_sve_s8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "cbz %x[bias], 1f\n" "ptrue p8.s\n" "1:" // No bias - "2:" // Loop "cntp x20, p2, p1.s\n" "whilelt p0.b, XZR, x20\n" diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_u8q_3x3_dot.cpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_u8q_3x3_dot.cpp index e5bc8198f8..7c5d3c4904 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_u8q_3x3_dot.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/sve_u8q_3x3_dot.cpp @@ -25,8 +25,8 @@ #if defined(ARM_COMPUTE_ENABLE_SVE) #include "arm_gemm.hpp" -#include "src/core/NEON/kernels/arm_gemm/utils.hpp" -#include "src/core/NEON/kernels/assembly/depthwise.hpp" +#include "utils.hpp" +#include "depthwise.hpp" #include <cstdint> namespace arm_conv { @@ -76,7 +76,6 @@ void interleave_sve_u8q_3x3_dot::pack_parameters(unsigned int n_channels, void * "cbz %x[bias], 1f\n" "ptrue p8.s\n" "1:" // No bias - "2:" // Loop "cntp x20, p2, p1.s\n" "whilelt p0.b, XZR, x20\n" |