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author | Giorgio Arena <giorgio.arena@arm.com> | 2021-02-08 13:20:24 +0000 |
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committer | Giorgio Arena <giorgio.arena@arm.com> | 2021-02-09 15:29:14 +0000 |
commit | 9f7d55a3566b0f1044110000b033d663b26d3a6c (patch) | |
tree | 25e40d85f91a9322d7840442fc9b27b8517a1651 /src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp | |
parent | 7b4278627ef04fb1fb136fe2a367bb67c97218d1 (diff) | |
download | ComputeLibrary-9f7d55a3566b0f1044110000b033d663b26d3a6c.tar.gz |
Fix CLDepthwiseConvolutionLayer 3x3 QASYMM8
Fix errors when computing tensors with one element only
- Replace Tensor3D with raw pointers so to get rid of offset to first element for NCHW layout
- Add stronger out of bound constraints for NHWC layout
- Set the border size to the input's padding for NHWC
- Fill the strides == 0 with the largest stride, so to avoid accessing empty strides and multiplying by 0
Resolve COMPMID-4088
Change-Id: I751a4e6d7094b3c42306ff7f53af848fd35f19ac
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5024
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Manuel Bottini <manuel.bottini@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp')
-rw-r--r-- | src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp b/src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp index f553fd1849..43c3ff3bfd 100644 --- a/src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp +++ b/src/core/CL/kernels/CLDepthwiseConvolutionLayer3x3NHWCKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020 Arm Limited. + * Copyright (c) 2018-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -233,7 +233,7 @@ void CLDepthwiseConvolutionLayer3x3NHWCKernel::configure(const CLCompileContext if(_is_quantized) { - _border_size = BorderSize(is_stride_1 ? 0 : conv_info.pad_left(), 0, std::max(std::max(conv_info.pad_right(), conv_info.pad_bottom()), conv_info.pad_top()), 0); + _border_size = BorderSize(input->info()->padding()); // If QASYMM8 and the 8 bit dot product is available, force _num_planes_processed_per_iteration to 1 if(is_dot8_supported) |