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| author | Sang-Hoon Park <sang-hoon.park@arm.com> | 2020-11-13 13:44:13 +0000 |
|---|---|---|
| committer | Sang-Hoon Park <sang-hoon.park@arm.com> | 2020-11-18 12:25:16 +0000 |
| commit | 75eea338eb232ebdafa2fb84d22e711b5f964785 (patch) | |
| tree | d069d26864c3ae180ff526262a1436af839a5bb0 /src/core/CL/cl_kernels/elementwise_operation.cl | |
| parent | 10a73f5c0cc15ffba532bc923c6471f67af0959a (diff) | |
| download | ComputeLibrary-75eea338eb232ebdafa2fb84d22e711b5f964785.tar.gz | |
COMPMID-3961: Add Logical OR/AND/NOT operator on CL
Change-Id: I612aeed6affa17624fb9044964dd59c41a5c9888
Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4448
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/CL/cl_kernels/elementwise_operation.cl')
| -rw-r--r-- | src/core/CL/cl_kernels/elementwise_operation.cl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/core/CL/cl_kernels/elementwise_operation.cl b/src/core/CL/cl_kernels/elementwise_operation.cl index f6c09b4ec7..ea25082a6c 100644 --- a/src/core/CL/cl_kernels/elementwise_operation.cl +++ b/src/core/CL/cl_kernels/elementwise_operation.cl @@ -40,6 +40,11 @@ #define POWER(x, y) pow(x, y) #define PRELU(x, y) (select(y * x, x, CONVERT((x > (DATA_TYPE_OUT)0), SELECT_VEC_DATA_TYPE(DATA_TYPE_OUT, VEC_SIZE_OUT)))) +#if defined(VEC_SIZE_OUT) && defined(DATA_TYPE_OUT) +#define AND(x, y) (CONVERT((x && y), VEC_DATA_TYPE(DATA_TYPE_OUT, VEC_SIZE_OUT)) & 1) +#define OR(x, y) (CONVERT((x || y), VEC_DATA_TYPE(DATA_TYPE_OUT, VEC_SIZE_OUT)) & 1) +#endif // defined(VEC_SIZE_OUT) && defined(DATA_TYPE_OUT) + #define OP_FUN_NAME_STR(op) elementwise_operation_##op #define OP_FUN_NAME(op) OP_FUN_NAME_STR(op) |