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This patch adjusts reference model for attribute name changes in
tosa.fb schema, and for obsoleted slice/tile/reshape attributes
also updated examples due to the breaking tosa flatbuffers changes
Signed-off-by: Tai Ly <tai.ly@arm.com>
Change-Id: I105eb99a4c35f289c5078aed0a7f9cbb6dfe9123
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- The previous ref_model was allocating the memory for all tensors in
the graph upfront which is unnecessary and wasteful.
- This patch changes to only allocate initial input tensors on the entry
point using the allocateInputTensor() function.
- The output tensors are ensured to have been allocated before executing
a node. The output tenosrs are the inputs for the next node.
- When a node's evaluation is finished, its input tensors will be freed
if they will no longer be used by anyone else.
Signed-off-by: Jerry Ge <jerry.ge@arm.com>
Change-Id: Ibb3e8c9e6344f6cd9eb20532a03b2097b93247f9
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- Also added run clang-format to pre-commit runs
Signed-off-by: Jerry Ge <jerry.ge@arm.com>
Change-Id: I4e59ac0afbaa30dce0773aa63d92a1a3b119e2f3
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Comparison operators produce boolean outputs, which need to be written into client data
Allow subgraph traverser to use main block to look for tensors when serialization handler is missing
Signed-off-by: Jiacheng Liang <jiacheng.liang@arm.com>
Change-Id: I6f9af470185541fa6466b3f7786c48f1555fa6f6
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This adds --precise_mode=1 option to tosa_referece_model,
which will cause reference model to convert all floating point tensors
to FP64 tensors and compute all operators accordingly.
Also adds optional -p arguments to test runners tosa_verif_run_tests.py
and tosa_verif_framework_compiler_runner.py to run tests in precise mode
Signed-off-by: Tai Ly <tai.ly@arm.com>
Change-Id: I156055216ad61710096497a8fa1a653be2a602a3
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This allows IF/WHILE serialization to use regions
instead of blocks to serialize nested regions.
For backward compatibility, both region and block
serialization are supported for IF/WHILE ops.
Signed-off-by: Tai Ly <tai.ly@arm.com>
Change-Id: Icf935561f9f5db38767ff76410bcd36896119395
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Rationale for making this change:
- In the original design, for control flow operators like WhileOp,
child blocks couldn't read the tensor variables (global consts) in the root level block,
this patch added the machanism for child blocks to access their parent
level block's tensors.
- This change also relies on another serialization change on adding
another layer of abtraction called Region:
- Serialization patch: [region] Add TosaSerializationRegion to serialization_lib
- Updated the corresponding python version of the serialization code: TosaSerializerRegion to python version of serialization_lib
- This change also relies on the TOSA MLIR Translator change: Add RegionBuilder to TOSA MLIR Translator
- Added the WhileOp related test cases: While, LSTM, GRU, RNN
- Other related fixes
Signed-off-by: Jerry Ge <jerry.ge@arm.com>
Change-Id: I13ae33628ad07e41d248e88652ce1328654694ab
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Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: Ifd771171904d1e5a9db3ea1cae3ac9017e971c8c
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- Also replace SIMPLE_FATAL_ERROR() with FATAL_ERROR() since they're duplicate
- Replace FATAL_ERROR()/ASSERT_MSG() with ERROR_IF_SUBGRAPH() if the condition is a graph error
FATAL_ERROR()/ASSERT() should only be used by model internal/runtime error like file reading.
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: If1e1e2488054a0ecd800fb0f2ea6487019282500
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or ERROR_IF()
- Adding return code enum class: {VALID, UNPREDICTABLE, ERROR}
- Runtime errors (e.g. memory allocation failure) will abort immediately, or will return one of the three return codes
Part of the codes are re-written to pass REQUIRE() to the top-level (e.g. apply_scale_32/16())
- Update setExpectedFailure() to setExpectedReturnCode() on test generation script
- Update test regression script to interface with reference model change
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: Ia063c936bcb2a54d6e379a5bb6801aa72d1186f1
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- remove identityN and placeholder
- add div
- update serialization_lib hash
- update apply_scale_16() assertion
- regenerate examples/ due to serialization_lib change
Change-Id: I7183d92bec33697c65adfc07cb8eb89c6882675a
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- Remove Usage and Format
- Run black on verif/*.py scripts
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: Ie81515891eb0039540f614894f4b6b0e0e78ba74
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Change-Id: I2f8e7fa63e2ae40203e57d2cc8814bde3b312cb6
Signed-off-by: Eric Kunze <eric.kunze@arm.com>
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