diff options
Diffstat (limited to 'source')
7 files changed, 234 insertions, 108 deletions
diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt index eebf235..9ccb9a4 100644 --- a/source/hal/source/components/npu/CMakeLists.txt +++ b/source/hal/source/components/npu/CMakeLists.txt @@ -17,7 +17,7 @@ #---------------------------------------------------------------------------- ######################################################### -# Ethos-U NPU initialization library # +# Arm Ethos-U NPU initialization library # ######################################################### cmake_minimum_required(VERSION 3.21.0) @@ -73,11 +73,20 @@ elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram) # Shared Sram can be used for Ethos-U55 and Ethos-U65 set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM") elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram) - # Dedicated Sram is used only for Ethos-U65 - if (ETHOS_U_NPU_ID STREQUAL U65) - list(APPEND ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}") + # Dedicated Sram is used only for Ethos-U65 and Ethos-U85 + if (ETHOS_U_NPU_ID STREQUAL U65 OR ETHOS_U_NPU_ID STREQUAL U85) + list( + APPEND + ETHOS_U_NPU_MEMORY_MODE_FLAG + "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" + "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}" + ) else () - message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.") + message( + FATAL_ERROR + "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. " + "`dedicated_sram` can be used only for Ethos-U65 or Ethos-U85." + ) endif () else () message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}") @@ -128,15 +137,20 @@ else() NPU_REGIONCFG_1=0) # AXI0=M0 for U55/U65 endif() -# Ethos-U55 supports a maximum burst length of 64 bytes while Ethos-U65 supports up to 128 bytes. +# Ethos-U55 supports a maximum burst length of 64 bytes, Ethos-U65 supports up to 128 bytes, +# and Ethos-U85 supports up to 256 bytes. # Although, this is system implementation dependent the platforms we build for should support the -# maximum burst length for both NPU configurations. +# maximum burst length for all NPU configurations. if (ETHOS_U_NPU_ID STREQUAL U65) target_compile_definitions(ethosu_core_driver PRIVATE AXI_LIMIT0_MAX_BEATS_BYTES=1 AXI_LIMIT1_MAX_BEATS_BYTES=1 AXI_LIMIT2_MAX_BEATS_BYTES=1 AXI_LIMIT3_MAX_BEATS_BYTES=1) # 0 = 64 byte burst & 1 = 128 byte burst +elseif (ETHOS_U_NPU_ID STREQUAL U85) + target_compile_definitions(ethosu_core_driver PRIVATE + AXI_LIMIT_SRAM_MAX_BEATS=2 + AXI_LIMIT_EXT_MAX_BEATS=2) # 0 = 64 byte burst, 1 = 128 byte burst, 2 = 256 byte burst endif() # Create static library diff --git a/source/hal/source/components/npu/ethosu_profiler.c b/source/hal/source/components/npu/ethosu_profiler.c index dea704c..77671a8 100644 --- a/source/hal/source/components/npu/ethosu_profiler.c +++ b/source/hal/source/components/npu/ethosu_profiler.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates * <open-source-office@arm.com> SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -79,6 +79,7 @@ void ethosu_pmu_init(void) /* Total counters = event counters + derived counters + total cycle count */ counters->num_total_counters = ETHOSU_PROFILER_NUM_COUNTERS; +#if defined(ETHOSU55) || defined(ETHOSU65) #if ETHOSU_PMU_NCOUNTERS >= 4 counters->npu_evt_counters[0].event_type = ETHOSU_PMU_NPU_ACTIVE; counters->npu_evt_counters[0].event_mask = ETHOSU_PMU_CNT1_Msk; @@ -102,6 +103,34 @@ void ethosu_pmu_init(void) #else /* ETHOSU_PMU_NCOUNTERS >= 4 */ #error "NPU PMU expects a minimum of 4 available event triggered counters!" #endif /* ETHOSU_PMU_NCOUNTERS >= 4 */ +#elif defined(ETHOSU85) +#if ETHOSU_PMU_NCOUNTERS >= 8 + counters->npu_evt_counters[0].event_type = ETHOSU_PMU_NPU_ACTIVE; + counters->npu_evt_counters[0].event_mask = ETHOSU_PMU_CNT1_Msk; + counters->npu_evt_counters[0].name = "NPU ACTIVE"; + counters->npu_evt_counters[0].unit = unit_cycles; + + counters->npu_evt_counters[1].event_type = ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED; + counters->npu_evt_counters[1].event_mask = ETHOSU_PMU_CNT2_Msk; + counters->npu_evt_counters[1].name = "NPU ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED"; + counters->npu_evt_counters[1].unit = unit_beats; + + counters->npu_evt_counters[2].event_type = ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN; + counters->npu_evt_counters[2].event_mask = ETHOSU_PMU_CNT3_Msk; + counters->npu_evt_counters[2].name = "NPU ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN"; + counters->npu_evt_counters[2].unit = unit_beats; + + counters->npu_evt_counters[3].event_type = ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED; + counters->npu_evt_counters[3].event_mask = ETHOSU_PMU_CNT4_Msk; + counters->npu_evt_counters[3].name = "NPU ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED"; + counters->npu_evt_counters[3].unit = unit_beats; + + counters->npu_evt_counters[4].event_type = ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN; + counters->npu_evt_counters[4].event_mask = ETHOSU_PMU_CNT5_Msk; + counters->npu_evt_counters[4].name = "NPU ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN"; + counters->npu_evt_counters[4].unit = unit_beats; +#endif /* ETHOSU_PMU_NCOUNTERS >= 8 */ +#endif /* defined(ETHOSU55) || defined(ETHOSU65) */ #if ETHOSU_DERIVED_NCOUNTERS >= 1 counters->npu_derived_counters[0].name = "NPU IDLE"; diff --git a/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template index a1a2251..d6cc79a 100644 --- a/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template +++ b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,45 +20,52 @@ #ifndef TIMING_ADAPTER_SETTINGS_H #define TIMING_ADAPTER_SETTINGS_H -#cmakedefine TA0_BASE (@TA0_BASE@) -#cmakedefine TA1_BASE (@TA1_BASE@) +#cmakedefine TA_SRAM0_BASE (@TA_SRAM0_BASE@) +#cmakedefine TA_SRAM1_BASE (@TA_SRAM1_BASE@) +#cmakedefine TA_SRAM2_BASE (@TA_SRAM2_BASE@) +#cmakedefine TA_SRAM3_BASE (@TA_SRAM3_BASE@) +#cmakedefine TA_EXT0_BASE (@TA_EXT0_BASE@) +#cmakedefine TA_EXT1_BASE (@TA_EXT1_BASE@) -/* Timing adapter settings for AXI0 */ -#if defined(TA0_BASE) +/* Timing adapter settings for SRAM */ +#if defined(TA_SRAM0_BASE) \ + || defined(TA_SRAM1_BASE) \ + || defined(TA_SRAM2_BASE) \ + || defined(TA_SRAM3_BASE) -#define TA0_MAXR (@TA0_MAXR@) -#define TA0_MAXW (@TA0_MAXW@) -#define TA0_MAXRW (@TA0_MAXRW@) -#define TA0_RLATENCY (@TA0_RLATENCY@) -#define TA0_WLATENCY (@TA0_WLATENCY@) -#define TA0_PULSE_ON (@TA0_PULSE_ON@) -#define TA0_PULSE_OFF (@TA0_PULSE_OFF@) -#define TA0_BWCAP (@TA0_BWCAP@) -#define TA0_PERFCTRL (@TA0_PERFCTRL@) -#define TA0_PERFCNT (@TA0_PERFCNT@) -#define TA0_MODE (@TA0_MODE@) -#define TA0_HISTBIN (@TA0_HISTBIN@) -#define TA0_HISTCNT (@TA0_HISTCNT@) +#define SRAM_MAXR (@SRAM_MAXR@) +#define SRAM_MAXW (@SRAM_MAXW@) +#define SRAM_MAXRW (@SRAM_MAXRW@) +#define SRAM_RLATENCY (@SRAM_RLATENCY@) +#define SRAM_WLATENCY (@SRAM_WLATENCY@) +#define SRAM_PULSE_ON (@SRAM_PULSE_ON@) +#define SRAM_PULSE_OFF (@SRAM_PULSE_OFF@) +#define SRAM_BWCAP (@SRAM_BWCAP@) +#define SRAM_PERFCTRL (@SRAM_PERFCTRL@) +#define SRAM_PERFCNT (@SRAM_PERFCNT@) +#define SRAM_MODE (@SRAM_MODE@) +#define SRAM_HISTBIN (@SRAM_HISTBIN@) +#define SRAM_HISTCNT (@SRAM_HISTCNT@) -#endif /* defined(TA0_BASE) */ +#endif /* defined(TA_SRAM0_BASE) */ -/* Timing adapter settings for AXI1 */ -#if defined(TA1_BASE) +/* Timing adapter settings for EXT */ +#if defined(TA_EXT0_BASE) || defined(TA_EXT1_BASE) -#define TA1_MAXR (@TA1_MAXR@) -#define TA1_MAXW (@TA1_MAXW@) -#define TA1_MAXRW (@TA1_MAXRW@) -#define TA1_RLATENCY (@TA1_RLATENCY@) -#define TA1_WLATENCY (@TA1_WLATENCY@) -#define TA1_PULSE_ON (@TA1_PULSE_ON@) -#define TA1_PULSE_OFF (@TA1_PULSE_OFF@) -#define TA1_BWCAP (@TA1_BWCAP@) -#define TA1_PERFCTRL (@TA1_PERFCTRL@) -#define TA1_PERFCNT (@TA1_PERFCNT@) -#define TA1_MODE (@TA1_MODE@) -#define TA1_HISTBIN (@TA1_HISTBIN@) -#define TA1_HISTCNT (@TA1_HISTCNT@) +#define EXT_MAXR (@EXT_MAXR@) +#define EXT_MAXW (@EXT_MAXW@) +#define EXT_MAXRW (@EXT_MAXRW@) +#define EXT_RLATENCY (@EXT_RLATENCY@) +#define EXT_WLATENCY (@EXT_WLATENCY@) +#define EXT_PULSE_ON (@EXT_PULSE_ON@) +#define EXT_PULSE_OFF (@EXT_PULSE_OFF@) +#define EXT_BWCAP (@EXT_BWCAP@) +#define EXT_PERFCTRL (@EXT_PERFCTRL@) +#define EXT_PERFCNT (@EXT_PERFCNT@) +#define EXT_MODE (@EXT_MODE@) +#define EXT_HISTBIN (@EXT_HISTBIN@) +#define EXT_HISTCNT (@EXT_HISTCNT@) -#endif /* defined(TA1_BASE) */ +#endif /* defined(TA_EXT0_BASE) */ #endif /* TIMING_ADAPTER_SETTINGS_H */ diff --git a/source/hal/source/components/npu_ta/ethosu_ta_init.c b/source/hal/source/components/npu_ta/ethosu_ta_init.c index 1ef4ff5..fc2b905 100644 --- a/source/hal/source/components/npu_ta/ethosu_ta_init.c +++ b/source/hal/source/components/npu_ta/ethosu_ta_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,62 +22,103 @@ #include "timing_adapter.h" /* Arm Ethos-U timing adapter driver header */ #include "timing_adapter_settings.h" /* Arm Ethos-U timing adapter settings */ +static uint32_t init_ta(uintptr_t base_addr, + struct timing_adapter_settings * ta_s, + char * name, + uint8_t idx) { + struct timing_adapter ta; + + if (0 != ta_init(&ta, base_addr)) { + printf_err("TA_%s%" PRIx8 " initialisation failed\n", name, idx); + return 1; + } + + ta_set_all(&ta, ta_s); + info("Configured TA_%s%" PRIx8 "\t@0x%" PRIx32 "\n", name, idx, base_addr); + return 0; +} + +static uint32_t init_sram_ta(uintptr_t base_addr, uint8_t idx) { + struct timing_adapter_settings ta_s = { + .maxr = SRAM_MAXR, + .maxw = SRAM_MAXW, + .maxrw = SRAM_MAXRW, + .rlatency = SRAM_RLATENCY, + .wlatency = SRAM_WLATENCY, + .pulse_on = SRAM_PULSE_ON, + .pulse_off = SRAM_PULSE_OFF, + .bwcap = SRAM_BWCAP, + .perfctrl = SRAM_PERFCTRL, + .perfcnt = SRAM_PERFCNT, + .mode = SRAM_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = SRAM_HISTBIN, + .histcnt = SRAM_HISTCNT + }; + + return init_ta(base_addr, &ta_s, "SRAM", idx); +} + + +static uint32_t init_ext_ta(uintptr_t base_addr, uint8_t idx) { + struct timing_adapter_settings ta_s = { + .maxr = EXT_MAXR, + .maxw = EXT_MAXW, + .maxrw = EXT_MAXRW, + .rlatency = EXT_RLATENCY, + .wlatency = EXT_WLATENCY, + .pulse_on = EXT_PULSE_ON, + .pulse_off = EXT_PULSE_OFF, + .bwcap = EXT_BWCAP, + .perfctrl = EXT_PERFCTRL, + .perfcnt = EXT_PERFCNT, + .mode = EXT_MODE, + .maxpending = 0, /* This is a read-only parameter */ + .histbin = EXT_HISTBIN, + .histcnt = EXT_HISTCNT + }; + + return init_ta(base_addr, &ta_s, "EXT", idx); +} + + int arm_ethosu_timing_adapter_init(void) { -#if defined(TA0_BASE) - struct timing_adapter ta_0; - struct timing_adapter_settings ta_0_settings = { - .maxr = TA0_MAXR, - .maxw = TA0_MAXW, - .maxrw = TA0_MAXRW, - .rlatency = TA0_RLATENCY, - .wlatency = TA0_WLATENCY, - .pulse_on = TA0_PULSE_ON, - .pulse_off = TA0_PULSE_OFF, - .bwcap = TA0_BWCAP, - .perfctrl = TA0_PERFCTRL, - .perfcnt = TA0_PERFCNT, - .mode = TA0_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA0_HISTBIN, - .histcnt = TA0_HISTCNT}; - - if (0 != ta_init(&ta_0, TA0_BASE)) { - printf_err("TA0 initialisation failed\n"); +#if defined(TA_SRAM0_BASE) + if (0 != init_sram_ta(TA_SRAM0_BASE, 0)) { return 1; } +#endif /* defined (TA_SRAM0_BASE) */ - ta_set_all(&ta_0, &ta_0_settings); - info("Configured TA0@0x%" PRIx32 "\n", TA0_BASE); -#endif /* defined (TA0_BASE) */ - -#if defined(TA1_BASE) - struct timing_adapter ta_1; - struct timing_adapter_settings ta_1_settings = { - .maxr = TA1_MAXR, - .maxw = TA1_MAXW, - .maxrw = TA1_MAXRW, - .rlatency = TA1_RLATENCY, - .wlatency = TA1_WLATENCY, - .pulse_on = TA1_PULSE_ON, - .pulse_off = TA1_PULSE_OFF, - .bwcap = TA1_BWCAP, - .perfctrl = TA1_PERFCTRL, - .perfcnt = TA1_PERFCNT, - .mode = TA1_MODE, - .maxpending = 0, /* This is a read-only parameter */ - .histbin = TA1_HISTBIN, - .histcnt = TA1_HISTCNT}; - - if (0 != ta_init(&ta_1, TA1_BASE)) - { - printf_err("TA1 initialisation failed\n"); +#if defined(TA_SRAM1_BASE) + if (0 != init_sram_ta(TA_SRAM1_BASE, 1)) { return 1; } +#endif /* defined (TA_SRAM1_BASE) */ - ta_set_all(&ta_1, &ta_1_settings); - info("Configured TA1@0x%" PRIx32 "\n", TA1_BASE); -#endif /* defined (TA1_BASE) */ +#if defined(TA_SRAM2_BASE) + if (0 != init_sram_ta(TA_SRAM2_BASE, 2)) { + return 1; + } +#endif /* defined (TA_SRAM2_BASE) */ + +#if defined(TA_SRAM3_BASE) + if (0 != init_sram_ta(TA_SRAM3_BASE, 3)) { + return 1; + } +#endif /* defined (TA_SRAM3_BASE) */ + +#if defined(TA_EXT0_BASE) + if (0 != init_ext_ta(TA_EXT0_BASE, 0)) { + return 1; + } +#endif /* defined (TA_EXT0_BASE) */ + +#if defined(TA_EXT1_BASE) + if (0 != init_ext_ta(TA_EXT1_BASE, 1)) { + return 1; + } +#endif /* defined (TA_EXT1_BASE) */ return 0; } diff --git a/source/hal/source/components/platform_pmu/include/platform_pmu.h b/source/hal/source/components/platform_pmu/include/platform_pmu.h index 09006dd..8077d31 100644 --- a/source/hal/source/components/platform_pmu/include/platform_pmu.h +++ b/source/hal/source/components/platform_pmu/include/platform_pmu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +24,7 @@ extern "C" { #include <stdint.h> #include <stdbool.h> -#define NUM_PMU_COUNTERS (10) /**< Maximum number of available counters. */ +#define NUM_PMU_COUNTERS (12) /**< Maximum number of available counters. */ /** * @brief Container for a single unit for a PMU counter. diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt index 4f77bdd..672cbcd 100644 --- a/source/hal/source/platform/mps3/CMakeLists.txt +++ b/source/hal/source/platform/mps3/CMakeLists.txt @@ -35,23 +35,59 @@ endif() if (TARGET_SUBSYSTEM STREQUAL sse-300) set(UART0_BASE "0x49303000" CACHE STRING "UART base address") set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") - set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U55 Interrupt") set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable") set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") - if (ETHOS_U_SEC_ENABLED) - set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") - if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") + if (ETHOS_U_NPU_ID STREQUAL U85) + if(ETHOS_U_NPU_CONFIG_ID MATCHES "^[A-Z]([0-9]+$)") + set(ETHOSU_MACS ${CMAKE_MATCH_1}) + else() + message(FATAL_ERROR "Couldn't work out Ethos-U number of MACS from ${ETHOS_U_NPU_CONFIG_ID}") endif() + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x58104000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_SRAM1_BASE "0x58104200" CACHE STRING "Ethos-U NPU timing adapter SRAM1") + if(ETHOSU_MACS STREQUAL "2048") + set(TA_SRAM2_BASE "0x58104400" CACHE STRING "Ethos-U NPU timing adapter SRAM2") + set(TA_SRAM3_BASE "0x58104600" CACHE STRING "Ethos-U NPU timing adapter SRAM3") + endif() + set(TA_EXT0_BASE "0x58104800" CACHE STRING "Ethos-U NPU timing adapter EXT0") + if(ETHOSU_MACS STREQUAL "1024" OR ETHOSU_MACS STREQUAL "2048") + set(TA_EXT1_BASE "0x58104A00" CACHE STRING "Ethos-U NPU timing adapter EXT1") + endif() + endif() + else () + set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x48104000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_SRAM1_BASE "0x48104200" CACHE STRING "Ethos-U NPU timing adapter SRAM1") + if(ETHOSU_MACS STREQUAL "2048") + set(TA_SRAM2_BASE "0x48104400" CACHE STRING "Ethos-U NPU timing adapter SRAM2") + set(TA_SRAM3_BASE "0x48104600" CACHE STRING "Ethos-U NPU timing adapter SRAM3") + endif() + set(TA_EXT0_BASE "0x48104800" CACHE STRING "Ethos-U NPU timing adapter EXT0") + if(ETHOSU_MACS STREQUAL "1024" OR ETHOSU_MACS STREQUAL "2048") + set(TA_EXT1_BASE "0x48104A00" CACHE STRING "Ethos-U NPU timing adapter EXT1") + endif() + endif() + endif () else () - set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") - if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter 1") + if (ETHOS_U_SEC_ENABLED) + set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_EXT0_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter EXT0") + endif() + else () + set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address") + if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) + set(TA_SRAM0_BASE "0x48103000" CACHE STRING "Ethos-U NPU timing adapter SRAM0") + set(TA_EXT0_BASE "0x48103200" CACHE STRING "Ethos-U NPU timing adapter EXT0") + endif() endif() endif () endif() @@ -60,7 +96,6 @@ endif() if (TARGET_SUBSYSTEM STREQUAL sse-310) set(UART0_BASE "0x49303000" CACHE STRING "UART base address") set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate") - set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)") set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address") set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U55 Interrupt") diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt index e8bc14e..cfaa887 100644 --- a/source/hal/source/platform/simple/CMakeLists.txt +++ b/source/hal/source/platform/simple/CMakeLists.txt @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,8 +40,8 @@ set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enabl set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable") if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) - set(TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") - set(TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") + set(TA_SRAM0_BASE "0x58103000" CACHE STRING "Ethos-U NPU timing adapter 0") + set(TA_EXT0_BASE "0x58103200" CACHE STRING "Ethos-U NPU timing adapter 1") endif() # 2. Create static library |