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| author | Alex Tawse <alex.tawse@arm.com> | 2024-04-05 11:45:51 +0100 |
|---|---|---|
| committer | Alex Tawse <alex.tawse@arm.com> | 2024-05-20 09:27:19 +0100 |
| commit | 51928a3fd979a36e6c7a9f73bf0ed3bc8a8b7dfd (patch) | |
| tree | 266b4498781c93feebf44808a847f5f6c0c9941b /scripts/vela/default_vela.ini | |
| parent | e0829d313211e5bd0176a6bfef9e07056eb1bbbf (diff) | |
| download | ml-embedded-evaluation-kit-51928a3fd979a36e6c7a9f73bf0ed3bc8a8b7dfd.tar.gz | |
MLECO-4980: Adding Arm Ethos-U85 beta support
* Adds beta support for Ethos-U85.
* By default, models will be compiled for
U85-512 as well as the existing U55-128
and U65-256 MAC configurations.
* All U85 MAC configurations are supported.
Change-Id: If11f09c581084b27cf02a91eb74b2b094fe70c3e
Signed-off-by: Alex Tawse <alex.tawse@arm.com>
Diffstat (limited to 'scripts/vela/default_vela.ini')
| -rw-r--r-- | scripts/vela/default_vela.ini | 69 |
1 files changed, 67 insertions, 2 deletions
diff --git a/scripts/vela/default_vela.ini b/scripts/vela/default_vela.ini index 9d6baa7..5d4d48e 100644 --- a/scripts/vela/default_vela.ini +++ b/scripts/vela/default_vela.ini @@ -1,5 +1,5 @@ ; -; SPDX-FileCopyrightText: Copyright 2021 Arm Limited and/or its affiliates <open-source-office@arm.com> +; SPDX-FileCopyrightText: Copyright 2021, 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); @@ -48,6 +48,71 @@ Dram_clock_scale=0.234375 Dram_burst_length=128 Dram_read_latency=500 Dram_write_latency=250 + +; SRAMx2 (16 GB/s) and DRAMx1 (3.75 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Low] +core_clock=500e6 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=16 +Sram_write_latency=16 +Dram_clock_scale=0.46875 +Dram_ports_used=1 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx2 (32 GB/s) and DRAM (12 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Mid_512] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=1 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx2 (32 GB/s) and DRAMx2 (24 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_Mid_1024] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=2 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=2 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + +; SRAMx4 (64 GB/s) and DRAMx2 (24 GB/s) +[System_Config.Ethos_U85_SYS_DRAM_High_2048] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_ports_used=4 +Sram_burst_length=64 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.75 +Dram_ports_used=2 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 + ; ----------------------------------------------------------------------------- ; Memory Mode @@ -64,4 +129,4 @@ cache_mem_area=Axi0 const_mem_area=Axi1 arena_mem_area=Axi1 cache_mem_area=Axi0 -arena_cache_size=393216
\ No newline at end of file +arena_cache_size=393216 |