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authorDiqing Zhong <diqing.zhong@arm.com>2020-12-11 13:07:37 +0100
committerpatrik.gustavsson <patrik.gustavsson@arm.com>2020-12-16 16:46:31 +0000
commitf842b69d007e70d70fc5cef3b6f1f50b4cabbd90 (patch)
tree0757948e7b4eeb8f3f9da70b05ef205b5ac5c255 /ethosu/vela/tensor.py
parent7a6f8438aaf750380a9fff799ca81ff5c7e2ae43 (diff)
downloadethos-u-vela-f842b69d007e70d70fc5cef3b6f1f50b4cabbd90.tar.gz
MLBEDSW-3465: Add memory settings into sys config
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com> Change-Id: I4a5c53d0c5957595fc639b174b2b227ea043d409
Diffstat (limited to 'ethosu/vela/tensor.py')
-rw-r--r--ethosu/vela/tensor.py17
1 files changed, 17 insertions, 0 deletions
diff --git a/ethosu/vela/tensor.py b/ethosu/vela/tensor.py
index de97710a..257cb5ff 100644
--- a/ethosu/vela/tensor.py
+++ b/ethosu/vela/tensor.py
@@ -19,6 +19,7 @@ import copy
import enum
import uuid
from collections import defaultdict
+from enum import auto
from functools import lru_cache
from typing import Dict
from typing import List
@@ -62,6 +63,22 @@ class MemType(enum.IntFlag):
return self.name
+class BandwidthDirection(enum.IntEnum):
+ Read = 0
+ Write = auto()
+ Size = auto()
+
+ def display_name(self):
+ return self.name
+
+ def identifier_name(self):
+ return self.name.lower()
+
+ @staticmethod
+ def all():
+ return (BandwidthDirection.Read, BandwidthDirection.Write)
+
+
class MemArea(enum.IntFlag):
Unknown = 0
Sram = 1