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| author | Tim Hall <tim.hall@arm.com> | 2020-06-15 20:47:35 +0100 |
|---|---|---|
| committer | Tim Hall <tim.hall@arm.com> | 2020-06-18 17:53:52 +0100 |
| commit | c30f495dc013a73e371dd8053a0381e4707ab309 (patch) | |
| tree | 902ded0cf05e6d00eb0d1a1f9c1464a1052def92 /ethosu/vela/npu_serialisation.py | |
| parent | 0fc46dc565b6991409169cc40fe9ac74237857fa (diff) | |
| download | ethos-u-vela-c30f495dc013a73e371dd8053a0381e4707ab309.tar.gz | |
Code clean-up using black and flake8
- No functional change
Signed-off-by: Tim Hall <tim.hall@arm.com>
Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc
Diffstat (limited to 'ethosu/vela/npu_serialisation.py')
| -rw-r--r-- | ethosu/vela/npu_serialisation.py | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/ethosu/vela/npu_serialisation.py b/ethosu/vela/npu_serialisation.py index 0cb40ed0..08dc0d38 100644 --- a/ethosu/vela/npu_serialisation.py +++ b/ethosu/vela/npu_serialisation.py @@ -46,11 +46,13 @@ def copy_compressed_values_to_memory_tensor(memory_tensor, src_tensor): memory_tensor.values[start_addr:end_addr] = compressed_values start_addr = end_addr + def copy_ifm_values_to_memory_tensor(memory_tensor, src_tensor): start_addr = src_tensor.address end_addr = start_addr + src_tensor.quant_values.size memory_tensor.values[start_addr:end_addr] = src_tensor.quant_values + def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens): if sg.placement != PassPlacement.Npu: return scratch_tens, flash_tens @@ -95,7 +97,7 @@ def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens) for cps in sg.cascaded_passes: for ps in cps.passes: if ps.placement == PassPlacement.Npu: - if ps.weight_tensor != None: + if ps.weight_tensor is not None: # For DMA ops, ps.weight_tensor is referring to the SRAM weight tensor and therefore the address # is pointing at the destination address of where the weights should be placed in SRAM. # This ensures that the Flash weight tensor is used instead and thus gets the correct address. @@ -106,9 +108,9 @@ def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens) copy_compressed_values_to_memory_tensor(sg.flash_tensor, ps.scale_tensor) - if ps.ifm_tensor != None and ps.ifm_tensor.mem_area != MemArea.Sram: + if ps.ifm_tensor is not None and ps.ifm_tensor.mem_area != MemArea.Sram: copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm_tensor) - if ps.ifm2_tensor != None and ps.ifm2_tensor.mem_area != MemArea.Sram: + if ps.ifm2_tensor is not None and ps.ifm2_tensor.mem_area != MemArea.Sram: copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm2_tensor) sg.command_stream_tensor = make_memory_tensor( |