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authorLouis Verhaard <louis.verhaard@arm.com>2020-08-05 16:11:29 +0200
committerLouis Verhaard <louis.verhaard@arm.com>2020-08-17 15:10:21 +0200
commit0b8268a0dac80aa22133ca83ed6912d3b565439a (patch)
tree159fe485c156d6a3f3a1a65ab1b1a24ff68f2849 /ethosu/vela/insert_dma.py
parent458a208c44f70a9848f1e8e2e91f28ce3641c48f (diff)
downloadethos-u-vela-0b8268a0dac80aa22133ca83ed6912d3b565439a.tar.gz
MLBEDSW-2688: Improved LUT support
- Support for more than one 256-byte LUT in SHRAM - No DMA is performed for a LUT that is already located in SHRAM - Added MemArea.Shram, used for LUT, to avoid false address collision asserts during SRAM tensor allocation - Added read access to LUT in memory access calculation Change-Id: If4d1eded5ed029d253f4f5efb2d80495fc3eac99 Signed-off-by: Louis Verhaard <louis.verhaard@arm.com>
Diffstat (limited to 'ethosu/vela/insert_dma.py')
-rw-r--r--ethosu/vela/insert_dma.py8
1 files changed, 1 insertions, 7 deletions
diff --git a/ethosu/vela/insert_dma.py b/ethosu/vela/insert_dma.py
index 6c5c8031..6cd2202c 100644
--- a/ethosu/vela/insert_dma.py
+++ b/ethosu/vela/insert_dma.py
@@ -61,13 +61,7 @@ def insert_dma_cmd(op, arch):
dma_cmd.attrs["destination"] = new_tens.mem_area
dma_cmd.run_on_npu = True
if tens.purpose == TensorPurpose.LUT:
- # TODO: Add support more than one LUT at a time
- # Reserve last 2 blocks for LUT
- if arch.shram_reserved_unused_banks == 0:
- arch.shram_reserved_unused_banks = 2
- arch.shram_total_banks -= arch.shram_reserved_unused_banks
- # Place the LUT in the last 2 blocks of SHRAM
- new_tens.address = arch.shram_bank_size * arch.shram_total_banks
+ new_tens.mem_area = MemArea.Shram
op.inputs[idx] = new_tens
return op