diff options
Diffstat (limited to 'targets/corstone-310')
-rw-r--r-- | targets/corstone-310/CMakeLists.txt | 23 | ||||
-rw-r--r-- | targets/corstone-310/target.cpp | 167 |
2 files changed, 2 insertions, 188 deletions
diff --git a/targets/corstone-310/CMakeLists.txt b/targets/corstone-310/CMakeLists.txt index d1c151f..2044c0c 100644 --- a/targets/corstone-310/CMakeLists.txt +++ b/targets/corstone-310/CMakeLists.txt @@ -1,6 +1,5 @@ # -# SPDX-FileCopyrightText: Copyright 2020-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> -# +# SPDX-FileCopyrightText: Copyright 2020-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the License); you may @@ -27,8 +26,6 @@ if (NOT CMAKE_TOOLCHAIN_FILE) endif() set(ETHOSU_TARGET_NPU_CONFIG "ethos-u55-256" CACHE STRING "NPU configuration") -set(ETHOSU_TARGET_NPU_COUNT 1 CACHE INTERNAL "Number of NPUs") -set(ETHOSU_TARGET_NPU_TA_COUNT 0 CACHE INTERNAL "Number of timing adapters per NPU") set(ETHOSU_PMU_EVENT_0 -1 CACHE STRING "PMU Event #0") set(ETHOSU_PMU_EVENT_1 -1 CACHE STRING "PMU Event #1") @@ -83,10 +80,6 @@ set(TRUSTZONE_BUILD OFF) add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../common target) target_compile_definitions(ethosu_target_common INTERFACE - # Configure NPU architecture and number of timing adapters - ETHOSU_NPU_COUNT=${ETHOSU_TARGET_NPU_COUNT} - ETHOSU_NPU_TA_COUNT=${ETHOSU_TARGET_NPU_TA_COUNT} - # Configure PMU events ETHOSU_PMU_EVENT_0=${ETHOSU_PMU_EVENT_0} ETHOSU_PMU_EVENT_1=${ETHOSU_PMU_EVENT_1} @@ -98,20 +91,6 @@ target_compile_definitions(ethosu_target_common INTERFACE ETHOSU_MODEL=$<STREQUAL:${MEMORY_MODEL},dram> ETHOSU_ARENA=$<STREQUAL:${MEMORY_ARENA},dram>) -# AXI Timing adaptors -set(registers MAXR MAXW MAXRW RLATENCY WLATENCY PULSE_ON PULSE_OFF BWCAP PERFCTRL PERFCNT MODE HISTBIN HISTCNT) - -foreach(register ${registers}) - foreach(index RANGE 0 1) - set(name ETHOSU_TA_${register}_${index}) - set(${name} -1 CACHE STRING "${name}") - - if (${name} GREATER_EQUAL 0) - target_compile_definitions(ethosu_target_common INTERFACE ${name}=${${name}}) - endif() - endforeach() -endforeach() - # Linker script set(LINK_FILE platform CACHE STRING "Link file") diff --git a/targets/corstone-310/target.cpp b/targets/corstone-310/target.cpp index ea20077..f946a74 100644 --- a/targets/corstone-310/target.cpp +++ b/targets/corstone-310/target.cpp @@ -1,6 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2020-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> - * + * SPDX-FileCopyrightText: Copyright 2020-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -24,7 +23,6 @@ #ifdef ETHOSU #include <ethosu_driver.h> -#include <timing_adapter.h> #endif #include "mpu.hpp" @@ -45,9 +43,6 @@ using namespace EthosU; #define ETHOSU_IRQ 16 #define ETHOSU_IRQ_PRIORITY 5 -#define ETHOSU0_TA0_BASE_ADDRESS 0x58103000 -#define ETHOSU0_TA1_BASE_ADDRESS 0x58103200 - /**************************************************************************** * Variables ****************************************************************************/ @@ -64,152 +59,6 @@ struct ethosu_driver ethosu0_driver; #endif /**************************************************************************** - * Timing Adapters - ****************************************************************************/ - -#ifdef ETHOSU - -#ifndef ETHOSU_TA_MAXR_0 -#define ETHOSU_TA_MAXR_0 0 -#endif - -#ifndef ETHOSU_TA_MAXW_0 -#define ETHOSU_TA_MAXW_0 0 -#endif - -#ifndef ETHOSU_TA_MAXRW_0 -#define ETHOSU_TA_MAXRW_0 0 -#endif - -#ifndef ETHOSU_TA_RLATENCY_0 -#define ETHOSU_TA_RLATENCY_0 0 -#endif - -#ifndef ETHOSU_TA_WLATENCY_0 -#define ETHOSU_TA_WLATENCY_0 0 -#endif - -#ifndef ETHOSU_TA_PULSE_ON_0 -#define ETHOSU_TA_PULSE_ON_0 0 -#endif - -#ifndef ETHOSU_TA_PULSE_OFF_0 -#define ETHOSU_TA_PULSE_OFF_0 0 -#endif - -#ifndef ETHOSU_TA_BWCAP_0 -#define ETHOSU_TA_BWCAP_0 0 -#endif - -#ifndef ETHOSU_TA_PERFCTRL_0 -#define ETHOSU_TA_PERFCTRL_0 0 -#endif - -#ifndef ETHOSU_TA_PERFCNT_0 -#define ETHOSU_TA_PERFCNT_0 0 -#endif - -#ifndef ETHOSU_TA_MODE_0 -#define ETHOSU_TA_MODE_0 1 -#endif - -#ifndef ETHOSU_TA_HISTBIN_0 -#define ETHOSU_TA_HISTBIN_0 0 -#endif - -#ifndef ETHOSU_TA_HISTCNT_0 -#define ETHOSU_TA_HISTCNT_0 0 -#endif - -#ifndef ETHOSU_TA_MAXR_1 -#define ETHOSU_TA_MAXR_1 0 -#endif - -#ifndef ETHOSU_TA_MAXW_1 -#define ETHOSU_TA_MAXW_1 0 -#endif - -#ifndef ETHOSU_TA_MAXRW_1 -#define ETHOSU_TA_MAXRW_1 0 -#endif - -#ifndef ETHOSU_TA_RLATENCY_1 -#define ETHOSU_TA_RLATENCY_1 0 -#endif - -#ifndef ETHOSU_TA_WLATENCY_1 -#define ETHOSU_TA_WLATENCY_1 0 -#endif - -#ifndef ETHOSU_TA_PULSE_ON_1 -#define ETHOSU_TA_PULSE_ON_1 0 -#endif - -#ifndef ETHOSU_TA_PULSE_OFF_1 -#define ETHOSU_TA_PULSE_OFF_1 0 -#endif - -#ifndef ETHOSU_TA_BWCAP_1 -#define ETHOSU_TA_BWCAP_1 0 -#endif - -#ifndef ETHOSU_TA_PERFCTRL_1 -#define ETHOSU_TA_PERFCTRL_1 0 -#endif - -#ifndef ETHOSU_TA_PERFCNT_1 -#define ETHOSU_TA_PERFCNT_1 0 -#endif - -#ifndef ETHOSU_TA_MODE_1 -#define ETHOSU_TA_MODE_1 1 -#endif - -#ifndef ETHOSU_TA_HISTBIN_1 -#define ETHOSU_TA_HISTBIN_1 0 -#endif - -#ifndef ETHOSU_TA_HISTCNT_1 -#define ETHOSU_TA_HISTCNT_1 0 -#endif - -#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2 -static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = { - {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}}; -struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT]; -struct timing_adapter_settings ethosu_ta_settings[ETHOSU_NPU_TA_COUNT] = {{ETHOSU_TA_MAXR_0, - ETHOSU_TA_MAXW_0, - ETHOSU_TA_MAXRW_0, - ETHOSU_TA_RLATENCY_0, - ETHOSU_TA_WLATENCY_0, - ETHOSU_TA_PULSE_ON_0, - ETHOSU_TA_PULSE_OFF_0, - ETHOSU_TA_BWCAP_0, - ETHOSU_TA_PERFCTRL_0, - ETHOSU_TA_PERFCNT_0, - ETHOSU_TA_MODE_0, - 0, // Read only register - ETHOSU_TA_HISTBIN_0, - ETHOSU_TA_HISTCNT_0}, - {ETHOSU_TA_MAXR_1, - ETHOSU_TA_MAXW_1, - ETHOSU_TA_MAXRW_1, - ETHOSU_TA_RLATENCY_1, - ETHOSU_TA_WLATENCY_1, - ETHOSU_TA_PULSE_ON_1, - ETHOSU_TA_PULSE_OFF_1, - ETHOSU_TA_BWCAP_1, - ETHOSU_TA_PERFCTRL_1, - ETHOSU_TA_PERFCNT_1, - ETHOSU_TA_MODE_1, - 0, // Read only register - ETHOSU_TA_HISTBIN_1, - ETHOSU_TA_HISTCNT_1}}; -#endif - -#endif - -/**************************************************************************** * Cache maintenance ****************************************************************************/ @@ -290,20 +139,6 @@ void targetSetup() { UartStdOutInit(); #ifdef ETHOSU - // Initialize timing adapter(s) - for (int i = 0; i < ETHOSU_NPU_COUNT; i++) { -#if defined(ETHOSU_TARGET_NPU_TA_COUNT) && ETHOSU_TARGET_NPU_TA_COUNT >= 2 - for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) { - if (ta_init(ðosu_ta[i][j], ethosu_ta_base_addrs[i][j])) { - printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i); - } else { - // Set the updated configuration - ta_set_all(ðosu_ta[i][j], ðosu_ta_settings[j]); - } - } -#endif - } - // Initialize Ethos-U NPU driver if (ethosu_init(ðosu0_driver, reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), |