diff options
| author | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-05-24 13:16:52 +0300 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2021-06-01 06:33:57 +0000 |
| commit | 3adfbc1bf472a095ef01e9f62f80d55e0d834dfe (patch) | |
| tree | bf6e3f6276469245fb2ce6d219dde3d333b3c507 /targets/corstone-300/platform.scatter | |
| parent | afadfc1ccb22fee7463c0f7b4daf467dabe98534 (diff) | |
| download | ethos-u-core-platform-3adfbc1bf472a095ef01e9f62f80d55e0d834dfe.tar.gz | |
Corstone-300 reduced SRAM size
Fix inconsistencies between the scatter file and linker script
Jira: MLBEDSW-4596
Change-Id: I4d31fc89ef0d0371e1ba8758d60871674cf844a9
Diffstat (limited to 'targets/corstone-300/platform.scatter')
| -rw-r--r-- | targets/corstone-300/platform.scatter | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index fe63d01..bf143dc 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -54,8 +54,8 @@ * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | - * | SSE-300 internal SRAM | 0x2100_0000 | 0x0040_0000 | NS | 2 banks of 2 MiB each; 3cc latency) | - * | SSE-300 internal SRAM | 0x3100_0000 | 0x0040_0000 | S | Secure alias for NS internal SRAM | + * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | + * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | * +-----------------------+-------------+-------------+----+--------------------------------------+ @@ -158,8 +158,7 @@ APP_IMAGE LR_START LR_SIZE .ANY1 (+RW +ZI) } - ; SSE-300 SRAM (3 cycles read latency) from M55/U55 - ; 2x2MB - only first part mapped + ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55 SRAM SRAM_START UNINIT SRAM_SIZE { #ifndef ETHOSU_FAST_MEMORY_SIZE |