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Base address 1 points at the TFLM arena and is by default routed
over AXI 0. For the spilling use case with both model and arena in
DRAM it would make more sense to route base addresses 0 and 1
over AXI 1.
For Ethos-U65 the default settings should correspond to the spilling
use case.
The AXI limits should have different max values depending on the NPU
architecture.
Change-Id: Icd317097e2cfdbfb39886e13c2cb2202651e5357
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Storing PMU counters in shadow variables, in case the PMU was powered
off or soft reset.
Change-Id: I64ccf3fb6195f9be2d8315891ec612bb75404885
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Allow user to define a base pointer offset, if the CPU and the NPU have
address spaces offseted from each other.
Soft reset NPU before every inference.
Added log prints.
Change-Id: I98a746d20dc780fefa23ad68816f5ba2ba2e6c6e
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Make ethosu_config.h define default macro's (with default
values) unless the user overrides them.
For CMake users, the macros can be defined on cmd line by
specifying CMAKE_C_FLAGS for cmake, like:
cmake ... -DCMAKE_C_FLAGS='-DFOO=1 -DBAR=2'
Change-Id: I20fd3e07fdcfb7cba58da7198fd986f8821902bb
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